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HMS30C7110 multipurpose network processor (arm based 32-bit microprocessor) datasheet version 1.5 magnachip semiconductor ltd.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 copyright. 2002 magnachip semiconductor inc. all rights reserved. no part of this publication may be copied in any form, by photocopy, microfilm, retrieval system, or by any other means now known or hereafter invented without the prior written permission of magnachip semiconductor inc. magnachip semiconductor inc. #1, hyangjeong-dong, heungduk-gu, cheongju-si, chungcheonbuk-do, republic of korea homepage: http://www.magnachip.com technical support homepage: will be construction as soon as possible h.q. of magnachip semiconductor inc. marketing site sales in korea telephone: 82-(0)43-270-4070 telephone: 82-(0)43-270-4085 telephone: 82-(0)2-3459-3738 facsimile: 82-(0)43-270-4099 facsimile: 82-(0)43-270-4099 facsimile: 82-(0)2-3459-3945 world wide sales network u.s.a. taiwan hong kong telephone: 1-408-232-8757 telephone: 886-(0)2-2500-8357 telephone: 852-2971-1640 facsimile: 1-408-232-8135 facsimile: 886-(0)2-2509-8977 facsimile: 852-2971-1622 HMS30C7110 datasheet, ver1.5 28 july. 03 magnachip semiconductor, corp. may make changes to specification and product description at any time without notice.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 revision history rev. 0.1 2002-07-31 first draft rev. 1.01 2002-10-31 rev. 1.1 2002-12-31 rev. 1.2 2003-03-17 correction on i/o and register map rev. 1.3 2003-04-13 correct ion on register description rev. 1.4 2003-07-18 correct ion on register description rev. 1.5 2003-07-28 add i/o pin description and add detail add ress add pll register map
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 contents 1. product overview .......................................................................................................... .........................12 1.1. summary of HMS30C7110? features ................................................................................................ .....13 1.2. block diagram .................................................................................................................. .......................16 1.3. pin assignments................................................................................................................ .......................17 1.4. package pin diagram (pq208) .................................................................................................... ............25 1.5. pin description................................................................................................................ .........................26 2. functional description ......................................................................................................... ..................30 2.1. system configuration ........................................................................................................... ...................32 2.1.1. power-up configuration......................................................................................................... .........32 2.1.2. system memory map .............................................................................................................. .......32 2.1.3. registers map .................................................................................................................. ...............35 2.1.4. arm7tdmi core .................................................................................................................. ........41 2.2. cache .......................................................................................................................... .............................42 2.2.1. architecture ................................................................................................................... .................42 2.2.2. user accessible regist ers (base = 0x1950_0000) ..........................................................................42 2.3. clock/watchdog timer ........................................................................................................... .................46 2.3.1. block diagram.................................................................................................................. ..............46 2.3.2. user accessible regist ers (base = 0x1830_0000) ..........................................................................47 2.4. memory controller (flash/rom) .................................................................................................. ..........52 2.4.1. block diagram.................................................................................................................. ..............52 2.4.2. user accessible regist ers (base = 0x1900_0000) ..........................................................................53 2.4.3. timing diagram................................................................................................................. .............56 2.5. memory controller (sdram)...................................................................................................... ...........57 2.5.1. block diagram.................................................................................................................. ..............57 2.5.2. user accessible regist ers (base = 0x1908_0000) ..........................................................................58 2.5.3. timing diagram................................................................................................................. .............63 2.6. ethernet mac................................................................................................................... .......................67 2.6.1. block diagram.................................................................................................................. ..............67
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 5 2.6.2. user accessible regist ers (base = 0x1920_0000) ..........................................................................70 2.7. uart........................................................................................................................... ............................95 2.7.1. block diagram.................................................................................................................. ..............96 2.7.2. user accessible regist ers (base = 0x1800_0000) ..........................................................................97 2.8. timer.......................................................................................................................... .........................108 2.8.1. user accessible regist ers (base = 0x1810_0000) ........................................................................108 2.9. gpio ........................................................................................................................... ...........................113 2.9.1. user accessible register s (base = 0x1820_0000) ........................................................................113 2.10. spi............................................................................................................................ ..............................117 2.10.1. block diagram.................................................................................................................. ............117 2.10.2. user accessible register s (base = 0x1840_0000) ........................................................................119 2.11. dma ............................................................................................................................ ..........................123 2.11.1. user accessible regist ers (base = 0x1910_0000) ........................................................................123 2.12. intc ........................................................................................................................... ...........................128 2.12.1. user accessible regist ers (base = 0x1930_0000) ........................................................................131 2.13. pcmcia controller .............................................................................................................. .................137 2.13.1. user accessible regist ers (base = 0x1940_0000) ........................................................................137 3. electrical characteristic s ..................... .......................... .......................... ................. ........... ................150 3.1. absolute maximum ratings....................................................................................................... ............150 3.2. recommended operating conditions ............................................................................................... .....150 3.3. dc characteristics ............................................................................................................. ....................151 3.4. ac characteristics ............................................................................................................. ....................152 3.4.1. clocks ......................................................................................................................... ..................152 3.4.2. sdram timing ................................................................................................................... ........153 3.4.3. ethernet timing (mii/100mbps) .................................................................................................. 154 3.4.4. ethernet timing (mii/10mbps) ................................................................................................... .155 3.4.5. ethernet timing (rmii)......................................................................................................... .......156 3.4.6. spi timing..................................................................................................................... ...............157 4. mechanical characterist ics .................. .......................... .......................... ................... ............ .............160 5. ordering information..................... ...................................................................................... ................161
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 6 figures figure 1.1 HMS30C7110 ? block diagram ................................................. ................ 16 figure 1.2 HMS30C7110 ? 208-pin pqfp assignment (top view)........................... 2 5 figure 2.1 block diagram of clock module ....................... ........................................ 46 figure 2.2 block diagram of external controller ................ ...................................... 53 figure 2.3 read cycle timing (setup = 4, access = 6, hold = 4) . .............................. 56 figure 2.4 write timin g (setup = 4, access = 6, hold = 4) ...... .................................. 56 figure 2.5 block diagram of sd ram controller................... ..................................... 58 figure 2.6 read/write cycle .................................... ................................................... 64 figure 2.7 refresh cycle ....................................... ...................................................... 64 figure 2.8 initialization timing ............................... ..................................................... 66 figure 2.9 block diagram of ethernet mac ....................... ....................................... 68 figure 2.10 block diagram of uart device ....................... ...................................... 96 figure 2.12 block diagram of spi ............................... ............................................. 118 figure 2.13 arbitration block diagram .......................... .......................................... 130 figure 3.1 sdram clock tim ing .................................. ............................................ 152 figure 3.2 mdc timing (ethernet) ............................... ............................................ 152 figure 3.3 spi clock timing .................................... ................................................. 152 figure 3.4 sdram timing diagram ................................ ......................................... 153 figure 3.5 ethernet mii timing diagram (100mbps) ............... ............................... 154 figure 3.6 ethernet mii timi ng diagram (10mbps)................ ................................. 155 figure 3.7 ethernet rmii timing diagram ........................ ....................................... 156 figure 3.8 spi timing diagram.................................. ............................................... 157 figure 4.1 mechanical characteristics .......................... ........................................... 160
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 7 tables table 1.1 pqfp pin list ........................................ ...................................................... 17 table 1.2 pin description...................................... ...................................................... 26 table 2.1 power-up configuration............................... .............................................. 32 table 2.2 system memory map : sdram_remap = 0 .................. ........................... 33 table 2.3 system memory map : sdram_remap = 1 .................. ........................... 34 table 2.4 register map at amba peri-bus........................ ....................................... 35 table 2.5 register map at amba host-bus........................ ...................................... 37 table 2.6 cache and write buffer control register .............. ................................... 42 table 2.7 registers for pll & watchdog timer................... .................................... 47 table 2.8 pll control.......................................... ........................................................ 47 table 2.9 watch dog timer control .............................. ............................................. 48 table 2.10 watch dog timer interval............................ ............................................ 48 table 2.11 main pll control.................................... .................................................. 49 table 2.12 pll status.......................................... ....................................................... 50 table 2.13 registers for rom controller........................ ........................................... 54 table 2.14 configuration registers bit definition.............. ....................................... 54 table 2.15 registers for sdram controller ...................... ........................................ 59 table 2.16 configuration register .............................. ................................................ 59 table 2.17 timing register ..................................... .................................................... 60 table 2.18 refresh interval .................................... .................................................... 61 table 2.19 init control register............................... ................................................. 62 table 2.20 address control register............................ .............................................. 63 table 2.21 initialization sequence............................. ................................................. 65 table 2.22 registers for ethernet mac.......................... ........................................... 71 table 2.23 mac mode register bit definition .................... ...................................... 73 table 2.24 interrupt source bit definition..................... ............................................ 75 table 2.25 interrupt enable bit definition ..................... ............................................ 76 table 2.26 inter-frame gap register............................ ............................................ 79 table 2.27 collision configuration definition .................. .......................................... 80 table 2.28 transmit buffer address............................. ............................................. 80
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 8 table 2.29 transmit buffer length.............................. .............................................. 81 table 2.30 receive buffer address .............................. ............................................. 81 table 2.31 receive frame status................................ ............................................... 82 table 2.32 receive buffer level................................ ................................................ 82 table 2.33 rx address return ................................... ................................................ 83 table 2.34 control mode register bit definition ................ ...................................... 83 table 2.35 mii mode register bit definition .................... ......................................... 84 table 2.36 mii command register definition ..................... ....................................... 85 table 2.37 mii transmit data register.......................... ............................................ 87 table 2.38 mii receive data register ........................... ............................................ 87 table 2.39 length register ..................................... ................................................... 87 table 2.40 multicast address (most significant) ................ ...................................... 88 table 2.41 multicast address (least significant) ............... ...................................... 88 table 2.42 mac address 0 (control & byte 5, 4) ................. ................................... 89 table 2.43 mac address 1 (byte 3, 2, 1, 0) ..................... ........................................ 89 table 2.44 pause frame address 0 ............................... ............................................ 90 table 2.45 pause frame address 1 ............................... ............................................ 91 table 2.46 pause frame type id and op code ..................... ................................... 91 table 2.47 pause frame delay value ............................. ............................................. 92 table 2.48 tx high priority queue base address................. ................................... 92 table 2.49 tx high priority queue length ....................... ........................................ 92 table 2.50 tx low priority queue level ......................... ......................................... 93 table 2.51 tx low priority queue address return ................ ................................. 93 table 2.52 tx high priority queue level ........................ ......................................... 94 table 2.53 tx high priority queue address return............... .................................. 94 table 2.54 registers for uart .................................. ................................................ 97 table 2.55 rhr bit definition.................................. ................................................... 98 table 2.56 thr bit definition .................................. .................................................. 98 table 2.57 ier bit definition .................................. .................................................... 99 table 2.58 iir bit definition .................................. ..................................................... 99 table 2.59 interrupt control functions......................... ........................................... 100 table 2.60 fcr bit definition .................................. ................................................. 101 table 2.61 lcr bit definition .................................. ................................................. 102
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 9 table 2.62 mcr bit definition .................................. ................................................ 103 table 2.63 autoflow control configuration ...................... ....................................... 103 table 2.64 lsr bit definition .................................. ................................................. 104 table 2.65 msr bit definition .................................. ................................................ 105 table 2.66 dll bit definition .................................. ................................................. 106 table 2.67 dlm bit definition .................................. ................................................ 107 table 2.68 registers for timer................................. .............................................. 108 table 2.69 clock selection register bit definition ............. .................................... 109 table 2.70 timer control register bit definition ............... .................................... 110 table 2.71 timer interval regis ter bit definition .............. ..................................... 110 table 2.72 current timer value register bit definition ......... ............................... 111 table 2.73 interrupt source register bit definition............ .................................... 111 table 2.74 interrupt enable .................................... .................................................. 112 table 2.75 registers for gpio.................................. ................................................ 113 table 2.76 gpo data register bit definition.................... ....................................... 114 table 2.77 gpi data register bit definition .................... ........................................ 114 table 2.78 gpio direction regis ter bit definition .............. .................................... 115 table 2.79 interrupt source register bit definition............ .................................... 115 table 2.80 the bit definition of the interrupt enable register . ............................ 116 table 2.81 interrupt mode register bit definition .............. .................................... 116 table 2.82 interrupt level register bit definition ............. ..................................... 116 table 2.89 registers for spi................................... .................................................. 119 table 2.90 spi control regist er bit definition................. ....................................... 120 table 2.91 configuration register bit definition ............... ..................................... 120 table 2.92 tx data register bit definition ..................... ........................................ 121 table 2.93 rx data register bit definition..................... ......................................... 121 table 2.94 interrupt source register bit definition............ .................................... 121 table 2.95 interrupt mask register bit definition .............. .................................... 122 table 2.96 spi status register bit definition.................. ........................................ 122 table 2.97 dma initial source register......................... .......................................... 123 table 2.98 dma initial destination register .................... ....................................... 124 table 2.99 dma control register ................................ ............................................ 124 table 2.100 dma status register ................................ ............................................ 125
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 10 table 2.101 dma mask trigger register.......................... ...................................... 126 table 2.102 interrupt source register.......................... ........................................... 129 table 2.103 source pending r egister ............................ .......................................... 132 table 2.104 interrupt mode register ............................ ........................................... 133 table 2.105 interrupt mask register ............................ ........................................... 133 table 2.106 priority register .................................. ................................................. 134 table 2.107 interrupt pending register......................... .......................................... 135 table 2.108 interrupt offset register .......................... ............................................ 136 table 2.109 registers for pcmcia ............................... ........................................... 137 table 2.110 registers for cardbus .............................. ............................................ 138 table 2.111 idr bit definition ................................. ................................................. 138 table 2.112 isr bit definition ................................. ................................................. 139 table 2.113 icr bit definition ................................. ................................................. 139 table 2.114 gcr bit definition................................. ................................................ 140 table 2.115 cscr bit definition ................................ .............................................. 141 table 2.116 ier bit definition ................................. ................................................. 141 table 2.117 setup bit definition ............................... ............................................... 142 table 2.118 command bit definition............................. ........................................... 142 table 2.119 recovery bit definition ............................ ............................................ 143 table 2.120 start address bit definition ....................... .......................................... 144 table 2.121 end address bit definition......................... .......................................... 144 table 2.122 gpio direction registers bit definition ............ ................................... 145 table 2.123 gpo registers bit definition ....................... ......................................... 145 table 2.124 gpi registers bit definition....................... ........................................... 145 table 2.125 gpio muxing table .................................. .............................................. 146 table 2.126 command bit definition............................. ........................................... 147 table 2.127 status bit definition.............................. ................................................ 148 table 2.128 retry time register bit definition ................. ....................................... 149 table 2.129 clk select register bit definition ................. ........................................ 149 table 3.1 absolute maximum ratings ............................. .......................................... 150 table 3.2 recommended operating conditions ..................... ................................... 150 table 3.3 dc characteristics................................... ................................................. 151 table 3.4 a.c. electrical characteristics...................... ........................................... 158
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 11
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 12 1. product overview the HMS30C7110? is a low-cost and high performance network processor for telecommunication equipments such as ip sharer, wireless local area network access point (wlan-ap), managed switch/bridge/hub, routers, and other devices that provide high-speed data networking. the HMS30C7110? includes an arm7tdmi processor with unified cache, and common network functions such as dual ethernet mac, pcmcia, and other common peripherals.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 13 1.1. summary of HMS30C7110? features system 32-bit arm7 processor core with cache high speed system bus & peripheral bus supports both big-endian / little-endian modes jtag-based debug solution cache 4k byte unified (data + instruction) 4-way set associative write back policy read miss fill up 8 word write buffer ethernet mac dual mac with 10/100base t mii, rmii and 7-wire interface 8 ethernet mac addresses internal loop-back mode allows programming of phy active level signal pad insertion for minimum frame size (64 bytes) programmable maximum frame length (up to 2000 bytes) dma controller 2-channel programmable dma uart dma support uart independent 2-channel tx/rx full duplex mode hardware flow control for one channel
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 14 16 byte internal rx/tx fifos to reduce data latency even, odd, forced one, and forced zero parity mode interrupt controller handles up to 32 interrupt sources supports hardware priority function programmable irq/fiq mode spi operates as master mode configurable address and data width timer three channels of 32-bit timer selectable channel clock speed gpio up to 13 gpi, 9 gpo (general purpose input output) ports supports external interrupt inputs memory controller supports up to three 4mb banks (flash/rom) and one 128mb bank (sdram) supports all major sdram/rom/flash memories supports 32-bit data width for sdram supports 8-bit, 16-bit, and 32-bit data width for flash/rom pcmcia controller supports 16-bit pc card host interface supports cardbus note: 16-bit pcmcia is designated as ?16-bit pc card? and 32-bit pcmcia as ?cardbus?. pc card is the card suitable for insertion in pcmcia slot. physical characteristics
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 15 operating voltage: core 2.5v, i/o 3.3v technology: 0.25um cmos operating temperature: 0 ~ 70 c operating frequency: 70 mhz package type: 208 pqfp
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 16 1.2. block diagram jtag pl l cl k arm7 tdmi system bus interrup t controller arbite r decode r pc card controller (16-bits , 32-bits) enet 0 dma 0 dma 1 enet 1 bu s bridge uart 0 gpio time r sp i arbite r decode r peripheral bus cache bus i/f cpu i/f uart 1 memc iic figure 1.1 HMS30C7110? block diagram
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 17 1.3. pin assignments table 1.1 pqfp pin list pin # pin name i o pad type description 1 mode i picd operation mode mode testse contents 0 0 normal operation 0 1 nandtree/bist/pll test 1 0 parallel capture for atpg 1 1 scan shift for atpg 2 testse i picd test scan enable. refer to the description for pin 1 3 nreset i pics system reset, active low 4 vssp p vss for io 5 mclk i pics sdram memory feedback clock 6 sclk o poc8a sdram clock 7 vssi p vss for core 8 addr21/endian bd pbcd8a address bus/endian at reset period. . pulled down internally over 50 kohm. 0: little endian (default) 1: big endian 9 addr20/boot32 bd pbcd8a address bus/boot32 at reset period. pulled down internally over 50 kohm. 0: 16-bit booting(default) 1: 32-bit booting 10 addr19/boot16-8 bu pbcu8a address bus/boot16-8 at reset. pulled up internally over 50 kohm. 0: 8-bit booting 1: 16-bit booting(default) 11 addr18/bypass bu pbcu8a address bus/bypass internal power-on-reset circuit. pulled up internally over 50 kohm. the active output width is over 1.5 sec when 10mhz main clock is used. 0: use internal power-on-reset ciruit 1: bypass internal power-on-reset circuit (default)
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 18 provide external 10 kohm pull-down to use internal reset 12 addr17 o poc8a address bus 13 vcci p vdd for core 14 addr16 o poc8a address bus 15 addr15 o poc8a address bus 16 addr14/ba1 o poc8a address bus/sdram bank address 1 17 addr13/ba0 o poc8a address bus/sdram bank address 0 18 addr12 o poc8a address bus 19 addr11 o poc8a address bus 20 vccp p vdd for io 21 addr10 o poc8a address bus 22 addr9 o poc8a address bus 23 addr8 o poc8a address bus 24 addr7 o poc8a address bus 25 addr6 o poc8a address bus 26 vssp p vss for io 27 addr5 o poc8a address bus 28 addr4 o poc8a address bus 29 addr3 o poc8a address bus 30 addr2 o poc8a address bus 31 addr1 o poc8a address bus 32 addr0 o poc8a address bus 33 vssi p vss for core 34 data31 bu pbcu8a data bus 35 data30 bu pbcu8a data bus 36 data29 bu pbcu8a data bus 37 data28 bu pbcu8a data bus 38 data27 bu pbcu8a data bus 39 data26 bu pbcu8a data bus 40 vssp p vss for io 41 data25 bu pbcu8a data bus 42 data24 bu pbcu8a data bus
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 19 43 data23 bu pbcu8a data bus 44 data22 bu pbcu8a data bus 45 data21 bu pbcu8a data bus 46 data20 bu pbcu8a data bus 47 vccp p vdd for io 48 data19 bu pbcu8a data bus 49 data18 bu pbcu8a data bus 50 data17 bu pbcu8a data bus 51 data16 bu pbcu8a data bus 52 data15 bu pbcu8a data bus 53 vssp p vss for io 54 data14 bu pbcu8a data bus 55 data13 bu pbcu8a data bus 56 data12 bu pbcu8a data bus 57 data11 bu pbcu8a data bus 58 data10 bu pbcu8a data bus 59 data9 bu pbcu8a data bus 60 vcci p vdd for core 61 data8 bu pbcu8a data bus 62 data7 bu pbcu8a data bus 63 data6 bu pbcu8a data bus 64 data5 bu pbcu8a data bus 65 data4 bu pbcu8a data bus 66 data3 bu pbcu8a data bus 67 vssi p vss for core 68 data2 bu pbcu8a data bus 69 data1 bu pbcu8a data bus 70 data0 bu pbcu8a data bus 71 nscs o poc8a sdram chip select 72 nras o poc8a row address strobe 73 ncas o poc8a column address strobe 74 nswe o poc8a sdram write enable
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 20 75 vccp p vdd for io 76 dqm3 o poc8a sdram data mask 3 77 dqm2 o poc8a sdram data mask 2 78 dqm1 o poc8a sdram data mask 1 79 dqm0 o poc8a sdram data mask 0 80 gpi[11] b pbc4a gpio input bit 11 81 gpi[12] b pbc4a gpio input bit 12 82 vcci p vdd for core 83 nrcs2 o poc4a rom/flash chip select 84 nrcs1 o poc4a rom/flash chip select 85 nrcs0 o poc4a rom/flash chip select 86 nroe o poc8a rom/flash output enable 87 nrwe o poc8a rom/flash write enable 88 vccp p vdd for io 89 e0_col/ /gpi[3] i pic collision/gpi[3] 90 e0_crs/e0_crsdv i pic carrier sense from the ethernet phy 91 e0_txd3/ gpo[5] o poc4a transmit data from the ethernet phy/gpo[5] 92 e0_txd2/gpo[4] o poc4a transmit data from the ethernet phy/gpo[4] 93 e0_txd1/ e0_txd1 o poc4a transmit data from the ethernet phy/ 94 e0_txd0/ e0_txd0 o poc4a transmit data from the ethernet phy 95 e0_txen/ e0_txen o poc4a transmit data enable to the ethernet phy 96 vssp p vss for io 97 e0_txclk i pics transmit clock from the ethernet phy 98 e0_txer/ gpo[3] o poc4a transmit data error to the ethernet phy/gpo[3] 99 e0_rxer/ e0_rxer i pic receive data error from the ethernet phy 100 e0_rxclk/e0_clk i pics receive clock from the ethernet phy 101 e0_rxdv/ gpi[6] i pic receive data valid from the ethernet phy/gpi[6] 102 e0_rxd0 /e0_rxd0 i pic receive data from the ethernet phy 103 e0_rxd1/ e0_rxd1 i pic receive data from the ethernet phy 104 e0_rxd2/ gpi[4] i pic receive data from the ethernet phy/gpi[4] 105 e0_rxd3/ gpi[5] i pic receive data from the ethernet phy/gpi[5] 106 e0_mdc o poc4a receive data from the ethernet phy
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 21 107 e0_mdio b pbcc4a receive data from the ethernet phy 108 pllvcc p vdd for pll 109 clki i posc1 main clock in for crystal (10~20mhz) 110 clko o posc1 main clock out for crystal (10~20mhz) 111 pllvss p vss for pll 112 e1_col/ gpi[7] i pic collision/gpi[7] 113 e1_crs/e1_crsdv i pic carrier sense from the ethernet phy 114 e1_txd3/ gpo[8] o poc4a transmit data from the ethernet phy/gpo[8] 115 e1_txd2/ gpo[7] o poc4a transmit data from the ethernet phy/gpo[7] 116 e1_txd1/ e1_txd1 o poc4a transmit data from the ethernet phy 117 e1_txd0/ e1_txd0 o poc4a transmit data from the ethernet phy 118 e1_txen/ e1_txen o poc4a transmit data enable to the ethernet phy 119 e1_txclk i pics transmit clock from the ethernet phy 120 e1_txer/ gpo[6] o poc4a transmit data error to the ethernet phy/gpo[6] 121 vssp p vss for io 122 e1_rxer/ e1_rxer i pic receive data error from the ethernet phy 123 e1_rxclk/ e1_clk i pics receive clock from the ethernet phy 124 e1_rxdv/ gpi[10] i pic receive data valid from the ethernet phy/gpi[10] 125 e1_rxd0/ e1_rxd0 i pic receive data from the ethernet phy 126 e1_rxd1/ e1_rxd1 i pic receive data from the ethernet phy 127 e1_rxd2/ gpi[8] i pic receive data from the ethernet phy/gpi[8] 128 e1_rxd3/ gpi[9] i pic receive data from the ethernet phy/gpi[9] 129 vccp p vdd for io 130 utxd o poc4a uart channel tx data 131 urxd i pic uart channel rx data 132 nccd_02/cdo b pbc4a cd1 input/ spi data output 133 nccd_01/cclk b pbc4a cd2 input/ spi clock output 134 cvs2/nccs b pbc4a vs 1/ spi chip select 135 cvs1/cdi b pbc4a vs 1/ spi data input 136 reset_ncrst o poc8a card reset 137 vssp p vss for io 138 nwait_ncserr/rxd bu pbcu4a wait from 16-bit pc card / rxdata for uart 1
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 22 139 nce2_cad10 bu pbcu4a chip enable 0 for 16-bit pc card/cardbus address data 140 nce1_ncbe0 bu pbcu4a chip enable for 16-bit pc card/cardbus cbe0 141 nwe_ncgnt bu pbcu4a write enable for 16-bit pc card /cardbus cgnt 142 noe_cad11 bu pbcu4a read enable for 16-bit pc card /cardbus address data 143 wp/niois16_ncclkru n bu pbcu4a write protect / io size 16 (*dma request for io mode 3)/cardbus cclkrun 144 nreg_ncbe3 / dack bu pbcu4a attribute memory select for 16-bit pc card / dma acknowledge 145 vcci p vdd for core 146 niord_cad13 bu pbcu4a i/o read for 16-bit pc card /cardbus address data 147 niowr_cad15 bu pbcu4a i/o write for 16-bit pc card /cardbus address data 148 ninpack_ncreq bu pbcu4a input acknowledge for 16-bit pc card (*dma request for io mode 2)/cardbus creq 149 nstschg_cstschg bu pbcu4a status change from 16-bit pc card / cts for uart 1 150 ready/nireq_ncint bu pbcu4a initialization ready from 16-bit pc card/cardbus interrupt request 151 d15_cad8 bu pbcu4a 16-bit pc card data/cardbus address data 152 vssi p vss for core 153 d14 bu pbcu4a 16-bit pc card data 154 d13_cad6 bu pbcu4a 16-bit pc card data/cardbus address data 155 d12_cad4 bu pbcu4a 16-bit pc card data/cardbus address data 156 d11_cad2 bu pbcu4a 16-bit pc card data/cardbus address data 157 d10_cad31 bu pbcu4a 16-bit pc card data/cardbus address data 158 d9_cad30 bu pbcu4a 16-bit pc card data/cardbus address data 159 vccp p vdd for io 160 d8_cad28 bu pbcu4a 16-bit pc card data/cardbus address data 161 d7_cad7 bu pbcu4a 16-bit pc card data/cardbus address data 162 d6_cad5 bu pbcu4a 16-bit pc card data/cardbus address data 163 d5_cad3 bu pbcu4a 16-bit pc card data/cardbus address data 164 d4_cad1 bu pbcu4a 16-bit pc card data/cardbus address data 165 d3_cad0 bu pbcu4a 16-bit pc card data/cardbus address data 166 vssi p vss for core 167 d2 bu pbcu4a 16-bit pc card data 168 d1_cad29 bu pbcu4a 16-bit pc card data/cardbus address data
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 23 169 d0_cad27 bu pbcu4a 16-bit pc card data/cardbus address data 170 a25_cad19/txd1 bu pbcu4a 16-bit pc card address/cardbus address data / txdata for uart 1 171 a24_cad17 bu pbcu4a 16-bit pc card address/cardbus address data 172 vssp p vss for io 173 a23_ncframe bu pbcu4a 16-bit pc card address/cardbus frame 174 a22_nctrdy bu pbcu4a 16-bit pc card address/cardbus trdy 175 a21_ncdevsel bu pbcu4a 16-bit pc card address/cardbus dev sel 176 a20_ncstop bu pbcu4a 16-bit pc card address/cardbus stop 177 a19_ncblock bu pbcu4a 16-bit pc card address/cardbus cblock 178 a18 b pbc4a 16-bit pc card address 179 a17_cad16 bu pbcu4a 16-bit pc card address/cardbus address data 180 vccp p vdd for io 181 a16_cclk b pbc8a 16-bit pc card address/cclk 182 a15_ncirdy bu pbcu4a 16-bit pc card address/cirdy 183 a14_ncperr bu pbcu4a 16-bit pc card address/cperr 184 a13_cpar bu pbcu4a 16-bit pc card address/cpar 185 a12_nccbe2 bu pbcu4a 16-bit pc card address/ccbe2 186 vcci p vdd for core 187 a11_cad12 bu pbcu4a 16-bit pc card address/cardbus address data 188 a10_cad9 bu pbcu4a 16-bit pc card address/cardbus address data 189 a9_cad14 bu pbcu4a 16-bit pc card address/cardbus address data 190 a8_nccbe1 bu pbcu4a 16-bit pc card address/cardbus ccbe1 191 a7_cad18 bu pbcu4a 16-bit pc card address/cardbus address data 192 a6_cad20 bu pbcu4a 16-bit pc card address/cardbus address data 193 vssp p vss for io 194 a5_cad21 bu pbcu4a 16-bit pc card address/cardbus address data 195 a4_cad22 bu pbcu4a 16-bit pc card address/cardbus address data 196 a3_cad23 bu pbcu4a 16-bit pc card address/cardbus address data 197 a2_cad24 bu pbcu4a 16-bit pc card address/cardbus address data 198 a1_cad25 bu pbcu4a 16-bit pc card address/cardbus address data 199 a0_cad26 bu pbcu4a 16-bit pc card address/cardbus address data 200 vccp p vdd for io
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 24 201 tms id picdd jtag test mode 202 tck i pics jtag clock 203 trst id picsd jtag reset 204 tdi iu picdu jtag data in 205 tdo o poc4a jtag data out 206 gpio2/wait b pbc4a gpio port/wait input 207 gpio1 b pbc4a gpio port 208 gpio0 b pbc4a gpio port note: io classification (weak pull-up and weak pull-down is pul l-up/down with over 50 kohm.) b: bidirectional, i: input, o:output, bu:bidire ctional with weak pull-up iu: input with weak pull-up, ou: output with weak pull -up, id: input with weak pull-down, bd: bidirectional with wea k pull-down
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 25 1.4. package pin diagram (pq208) vssp data[14] data[13] data[12] data[11] data[10] data[9] vddi data[8] data[7] data[6] data[5] data[4] data[3] vssi data[2] data[1] data[0] nscs nras ncas nswe vddp dqm[3] dqm[2] dqm[1] dqm[0] sda scl vddi nrcs[2] nrcs[1] nrcs[0] nroe nrwe vddp e0_col/gpi[3] e0_crs/e0_crs_dv e0_txd[3]/gpo[5] e0_txd[2]/gpo[4] e0_txd[1] e0_txd[0] e0_txen vssp e0_txclk e0_txer/gpo[3] e0_rxer e0_rxclk/e0_refclk e0_rxdv/gpi[6] e0_rxd[0] e0_rxd[1] e0_rxd[2]/gpi[4] 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 mode testse nreset vssp mclk sclk vssi addr[21]/endian addr[20]/boot32 addr[19]/boot16-8 addr[18]/bypass addr[17] vddi addr[16] addr[15] addr[14] addr[13] addr[12] addr[11] vddp addr[10] addr[9] addr[8] addr[7] addr[6] vssp addr[5] addr[4] addr[3] addr[2] addr[1] addr[0] vssi data[31] data[30] data[29] data[28] data[27] data[26] vssp data[25] data[24] data[23] data[22] data[21] data[20] vddp data[19] data[18] data[17] data[16] data[15] gpio[0] gpio[1] gpio[2] tdo tdi trst tck tms vddp raddr[0]/cad[26] raddr[1]/cad[25] raddr[2]/cad[24] raddr[3]/cad[23] raddr[4]/cad[22] raddr[5]/cad[21] vssp raddr[6]/cad[20] raddr[7]/cad[18] raddr[8]/nbe1 raddr[9]/cad[14] raddr[10]/cad[9] raddr[11]/cad[12] vddi raddr[12]/nbe2 raddr[13]/ncpar raddr[14]/ncperr raddr[15]/ncirdy raddr[16]/cclk vddp raddr[17]/cad[16] raddr[18]/rfu raddr[19]/ncblock raddr[20]/ncstop raddr[21]/ncdevsel cts/nctrdy rts/ncframe vssp rxd[1]/cad[17] txd[1]/cad[19] rdata[0]/cad[27] rdata[1]/cad[29] rdata[2] vssi rdata[3]/cad[0] rdata[4]/cad[1] rdata[5]/cad[3] rdata[6]/cad[5] rdata[7]/cad[7] rdata[8]/cad[28] vddp rdata[9]/cad[30] rdata[10]/cad[31] rdata[11]/cad[2] rdata[12]/cad[4] rdata[13]/cad[6] rdata[14] vssi rdata[15]/cad[8] nireq, ready/ncint nstschg ndreq, ninpack/ncreq niowr/cad15 niord/cad13 vddi nreg/nbe3 niois16/ncclkrun noe/cad11 nwe/ncgnt nce2/nbe0 nce1/cad10 nwait/ncserr vssp nresetout cdi/vs1 nccs/vs2 cclk/cd1 cdo/cd2 urxd utxd vddp e1_rxd[3]/gpi[9] e1_rxd[2]/gpi[8] e1_rxd[1] e1_rxd[0]] e1_rxdv/gpi[10] e1_rxclk/e1_refclk e1_rxer vssp e1_txer/gpo[6] e1_txclk e1_txen e1_txd[0] e1_txd[1] e1_txd[2]/gpo[7] e1_txd[3]/gpo[8] e1_crs/e0_crs_dv e1_col/gpi[7] pllvss clko clki pllvdd e0_mdio e0_mdc e0_rxd[3]/gpi[5] HMS30C7110 pq208 xxxx figure 1.2 HMS30C7110? 208-pin pqfp assignment (top view)
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 26 1.5. pin description table 1.2 pin description block port direction description mode i operation mode testse i test scan enable nreset i system reset, active low clki i main clock in for crystal (10~20mhz) system configuration (5) clko o main clock out for crystal (10~20mhz) mtxclk i transmit nibble or symbol clock from the phy mtxd[3:0] o transmit data nibble mtxen o transmit enable mtxerr o transmit coding error mrxclk i receive nibble or symbol clock from the phy mrxdv i receive data valid from the phy mrxd[3:0] i receive data nibble mrxerr i receive error from the phy mcoll i collision detected from the phy mcrs i carrier sense from the phy mdc i management data clock mdio i/o management data input/output e0_col i collision from the ethernet phy0 e0_crs i carrier sense from the ethernet phy0 e0_txd[3-0] o transmit data from the ethernet phy0 e0_txen o transmit data enable to the ethernet phy0 e0_txclk i transmit clock from the ethernet phy0 e0_txer o transmit data error to the ethernet phy0 e0_rxer i receive data error from the ethernet phy0 e0_rxclk i receive clock from the ethernet phy0 e0_rxdv i receive data valid from the ethernet phy0 ethernet mac (53) e0_rxd[3-0] i receive data from the ethernet phy0
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 27 e0_mdc o receive data from the ethernet phy0 e0_mdio b receive data from the ethernet phy0 e1_col i collision from the ethernet phy1 e1_crs i carrier sense from the ethernet phy e1_txd[3-0] o transmit data from the ethernet phy1 e1_txen o transmit data enable to the ethernet phy1 e1_txclk i transmit clock from the ethernet phy1 e1_txer o transmit data error to the ethernet phy1 e1_rxer i receive data error from the ethernet phy1 e1_rxclk i receive clock from the ethernet phy1 e1_rxdv i receive data valid from the ethernet phy1 e1_rxd[3-0] i receive data from the ethernet phy1 mclk i sdram memory feedback clock sclk o sdram clock nscs o sdram chip select nras o row address strobe ncas o column address strobe nswe o sdram write enable dqm3 o sdram data mask 3 dqm2 o sdram data mask 2 dqm1 o sdram data mask 1 dqm0 o sdram data mask 0 addr[21-0] b address bus sdram controller (64) data[31-0] b data bus nrcs[2-0] o rom/flash chip select nroe o rom/flash output enable nrwe o rom/flash write enable addr[21-0] b address bus flash/rom controller (59) data[31-0] b data bus nwait_ncserr i wait from 16-bit pc card / cardbus cserr pcmcia controller (53) nce2_cad10 o chip enable 0 for 16-bit pc card/cardbus address data
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 28 nce1_ncbe0 i chip enable 1 for 16-bit pc card/cardbus cbe0 nwe_ncgnt o write enable/cardbus cgnt noe_cad11 b read enable/cardbus address data wp/niois16_ncclkrun i write protect / io size 16 (*dma request for io mode 3) nreg_ncbe3 / dack o attribute memory select / dma acknowledge niord_cad13 b i/o read for 16-bit pc card/cardbus address data niowr_cad15 b i/o write for 16-bit pc card/cardbus address data ninpack_ncreq i input acknowledge (*dma request for io mode 2) nstschg_cstschg i status change from 16-bit pc card / cts for uart 1 ready/nireq_ncint i initialization ready from 16-bit pc card / cardbus interrupt request d15_cad8 b 16-bit pc card data/cardbus address data d14 b 16-bit pc card data d13_cad6 b 16-bit pc card data/cardbus address data d12_cad4 b 16-bit pc card data/cardbus address data d11_cad2 b 16-bit pc card data/cardbus address data d10_cad31 b 16-bit pc card data/cardbus address data d9_cad30 b 16-bit pc card data/cardbus address data d8_cad28 b 16-bit pc card data/cardbus address data d7_cad7 b 16-bit pc card data/cardbus address data d6_cad5 b 16-bit pc card data/cardbus address data d5_cad3 b 16-bit pc card data/cardbus address data d4_cad1 b 16-bit pc card data/cardbus address data d3_cad0 b 16-bit pc card data/cardbus address data d2 b 16-bit pc card data d1_cad29 b 16-bit pc card data/cardbus address data d0_cad27 b 16-bit pc card data/cardbus address data a25_cad19/txd1 b 16-bit pc card address/cardbus address data / txdata for uart 1 a24_cad17 b 16-bit pc card address/cardbus address data a23_ncframe b 16-bit pc card address/cardbus frame
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 29 a22_nctrdy b 16-bit pc card address/cardbus trdy a21_ncdevsel b 16-bit pc card address/cardbus dev sel a20_ncstop b 16-bit pc card address/cardbus stop a19_ncblock b 16-bit pc card address/cardbus cblock a18 b 16-bit pc card address a17_cad16 b 16-bit pc card address/cardbus address data a16_cclk b 16-bit pc card address/ cardbus cclk a15_ncirdy b 16-bit pc card address/ cardbus cirdy a14_ncperr b 16-bit pc card address/ cardbus cperr a13_cpar b 16-bit pc card address/ cardbus cpar a12_nccbe2 b 16-bit pc card address/ cardbus ccbe2 a11_cad12 b 16-bit pc card address/cardbus address data a10_cad9 b 16-bit pc card address/cardbus address data a9_cad14 b 16-bit pc card address/cardbus address data a8_nccbe1 b 16-bit pc card address/ cardbus ccbe1 a7_cad18 b 16-bit pc card address/cardbus address data a6_cad20 b 16-bit pc card address/cardbus address data a5_cad21 b 16-bit pc card address/cardbus address data a4_cad22 b 16-bit pc card address/cardbus address data a3_cad23 b 16-bit pc card address/cardbus address data a2_cad24 b 16-bit pc card address/cardbus address data a1_cad25 b 16-bit pc card address/cardbus address data a0_cad26 b 16-bit pc card address/cardbus address data utxd o tx data for uart channel0 urxd i rx data for uart channel0 a25_cad19/txd1 o tx data for uart channel1 nwait_ncserr/rxd i rx data for uart channel1 ninpack_ncreq i cts for uart 1 uart (6) nstschg_cstschg o rts for uart 1 gpi12-3 b gpio input gpo12-3 b gpio output gpio (21) gpio2-0 b gpio inout
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 30 cclk o spi clock output cdo o spi data output cdi o spi data input spi (4) nccs i spi chip select 2. functional description the following internal functions will be covered in this sectio n:
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 31 ? system configuration ? arm7tdmi core ? cache ? clock/watch-dog timer ? memory controller (f lash/sram/pcmcia) ? memory controller (sdram) ? ethernet ? uart ? timer ? gpio ? spi ? dma ? intc ? pcmcia controller
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 32 2.1. system configuration this section describes system memory map and power-up configuration of HMS30C7110?. 2.1.1. power-up configuration the following table shows power-up configuration mapping based on mode configuration pins (mode, testse). table 2.1 power-up configuration mode testse contents 0 0 normal operation 0 1 nandtree/bist/pll test 1 0 parallel capture for atpg 1 1 scan shift for atpg 2.1.2. system memory map the system memory map can be one of the following two configurations: 1. memory maps a. sdram_remap = 0 b. sdram_remap = 1 two different memory maps can be selected by one of memc (sdram) registers. refer to memc for details. note 1: this address range is repeated in 0x4000_0000 ~ 0x7fff_ffff, 0x8000_0000 ~ 0xbfff_ffff, and 0xc000_0000 ~ 0xffff_ffff. note 2: 0x0000_0000 ~ 0x7fff_ffff is cacheable area and 0x8000_0000 ~ 0xffff_ffff is non-
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 33 cacheable area. table 2.2 system memory map : sdram_remap = 0 base address size function 0x3e00_0000 32mb cardbus special cycle 0x3c00_0000 32mb cardbus configuration 0x3800_0000 64mb cardbus i/o 0x3000_0000 128mb cardbus memory 0x2c00_0000 64mb reserved 0x2800_0000 64mb attribute memory of pcmcia 0x2400_0000 64mb common memory of pcmcia 0x2000_0000 64mb i/o area of pcmcia 0x1960_0000 106mb reserved 0x1950_0000 1mb cache registers 0x1948_0000 0.5mb cardbus bridge registers 0x1940_0000 0.5mb pcmcia interface registers 0x1930_0000 1mb intc registers 0x1920_1000 996kb enet mac1 registers 0x1920_0000 4kb enet mac0 registers 0x1910_0000 1mb dma registers 0x1908_0000 0.5mb sdramc registers 0x1900_0000 0.5mb romc registers 0x1860_0000 10mb reserved 0x1850_0000 1mb reserved 0x1840_0000 1mb spi registers 0x1830_0000 1mb wdt/clkrst registers 0x1820_0000 1mb gpio registers 0x1810_0000 1mb timer registers 0x1808_0000 0.5mb uart1 registers 0x1800_0000 0.5mb uart0 registers 0x1000_0000 128mb sdram memory 0x0800_0000 128mb reserved 0x0200_0000 96mb reserved 0x0100_0000 16mb flash/io/sram bank-1 0x0000_0000 16mb flash/io/sram bank-0
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 34 table 2.3 system memory map : sdram_remap = 1 base address size function 0x3e00_0000 32mb cardbus special cycle 0x3c00_0000 32mb cardbus configuration 0x3800_0000 64mb cardbus i/o 0x3000_0000 128mb cardbus memory 0x2c00_0000 64mb reserved 0x2800_0000 64mb attribute memory of pcmcia 0x2400_0000 64mb common memory of pcmcia 0x2000_0000 64mb i/o area of pcmcia 0x1960_0000 106mb reserved 0x1950_0000 1mb cache registers 0x1940_0000 1mb card interface registers 0x1930_0000 1mb intc registers 0x1920_0000 1mb enet mac registers 0x1910_0000 1mb dma registers 0x1900_0000 1mb memc registers 0x1860_0000 10mb reserved 0x1850_0000 1mb reserved 0x1840_0000 1mb spi registers 0x1830_0000 1mb wdt/clkrst registers 0x1820_0000 1mb gpio registers 0x1810_0000 1mb timer registers 0x1808_0000 0.5mb uart1 registers 0x1800_0000 0.5mb uart0 registers 0x1200_0000 96mb reserved 0x1100_0000 16mb flash/io/sram bank-1 0x1000_0000 16mb flash/io/sram bank-0 0x0800_0000 128mb reserved 0x0000_0000 128mb sdram memory
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 35 2.1.3. registers map table 2.4 register map at amba peri-bus block address name r/w reset value 1800_0000 data fifo r/w xxxx_xxxx _0004 interrupt enable register r/w 0000_0000 _0008 interrupt identification register r/w 0000_0001 _000c line control register r/w 0000_0000 _0010 modem control register r/w 0000_0000 _0014 line status register r/w 0000_0000 _0018 modem status register r/w 0000_0000 uart0 0001c ? 7fffc reserved 0000_0000 1808_0000 data fifo r/w xxxx_xxxx _0004 interrupt enable register r/w 0000_0000 _0008 interrupt identification register r/w 0000_0001 _000c line control register r/w 0000_0000 _0010 modem control register r/w 0000_0000 _0014 line status register r/w 0000_0000 _0018 modem status register r/w 0000_0000 uart1 8001c ? ffffc reserved 0000_0000 1810_0000 input clock selection for 3 channels r/w 0000_0000 _0004 channel enable r/w 0000_0000 _0008 timer interval for ch0 r/w 0000_0000 _000c timer interval for ch1 r/w 0000_0000 _0010 timer interval for ch2 r/w 0000_0000 _0014 current timer value for ch0 r 0000_0000 _0018 current timer value for ch1 r 0000_0000 _001c current timer value for ch2 r 0000_0000 _0020 interrupt pending register r/w 0000_0000 _0024 interrupt enable r/w 0000_0000 timer 00028 ? ffffc reserved interrupt enable 1820_0000 general purpose output r/w 0000_0000 _0004 general purpose input r/w 0000_0000 gpio _0008 gpio direction (output enable) r/w 0000_0000
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 36 _000c interrupt pending register r/w 0000_0000 _0010 interrupt enable register r/w 0000_0000 _0014 interrupt mode register r/w 0000_0000 _0018 interrupt level register r/w 0000_0000 0001c ? ffffc reserved 0000_0000 1830_0000 pll control r/w 0000_0008 _0004 wdt control r/w 0000_0000 _0008 wdt counter r/w 0000_0000 _000c pll control r/w a006_0080 _0010 pll status r 0000_0000 clockrst 00014 ? ffffc reserved 0011_0000 1840_0000 spi control r/w 0000_0000 _0004 spi mode 0 r/w 0000_0000 _0008 reserved r/w _000c reserved r/w _0010 reserved r/w _0014 reserved r/w _0018 spi tx data w n/a _001c spi rx data (r) / rx flush (w) r/w 0000_00xx _0020 spi interrupt pending register r/w 0000_0000 _0024 spi interrupt enable register r/w 0000_0000 _0028 spi status register r 0000_0001 spi 0002c ? ffffc reserved 0000_0000 1850_0000 iic control register r/w 0000_0000 _0004 iic buffer register r/w xxxx_xxxx _0008 iic baud rate register r/w 0000_0000 _000c iic data length (in byte) r 0000_0000 _0010 iic device address r/w 0000_0000 iic 00014 ? ffffc reserved 0000_0000
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 37 table 2.5 register map at amba host-bus block address name r/w reset value 1900_0000 rom timing control for bank 0 r/w 0333_00ff _0004 rom timing control for bank 1 r/w 03ff_ffff _0008 rom timing control for bank 2 r/w 03ff_ffff rom controller 0000c ? 7fffc reserved 0000_0000 1908_0000 sdram configuration r/w 0000_003f _0004 reserved _0008 reserved _000c reserved _0010 sdram timing parameters r/w 7777_ff71 _0014 refresh interval value & mclk timing r/w 1303_0000 _0018 initialize start register r/w 0000_0000 _001c booting control register r/w 0000_0000 sdram controller 80020 ? 7fffc reserved 0000_0000 1910_0000 dma initial source register for channel 0 r/w 0000_0000 _0004 dma initial destination register for ch0 r/w 0000_0000 _0008 dma control register for ch0 r/w 0000_0000 _000c dma status register for ch0 r 0000_0000 _0010 dma current source register for ch0 r 0000_0000 _0014 dma current destination register for ch0 r 0000_0000 _0018 dma mask trigger register for ch0 r/w 0000_0000 _001c reserved _0020 dma initial source register for channel 1 r/w 0000_0000 _0024 dma initial destination register for ch 1 r/w 0000_0000 _0028 dma control register for ch 1 r/w 0000_0000 _002c dma status register for ch 1 r 0000_0000 _0030 dma current source register for ch 1 r 0000_0000 _0034 dma current destination register for ch 1 r 0000_0000 _0038 dma mask trigger register for ch 1 r/w 0000_0000 dma controller 0003c ? ffffc reserved 0000_0000
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 38 1920_0000 mac mode register r/w 0002_0630 _0004 interrupt source register r/w 0000_0000 _0008 interrupt mask register r/w 0000_0000 _000c inter-frame gap register r/w 0000_0018 _0010 collision control register r/w 000f_2010 _0014 transmit buffer base address low r/w 0000_0000 _0018 transmit buffer length low r/w 0000_0000 _001c receive buffer base address r/w 0000_0000 _0020 receive buffer status r 0000_0000 _0024 receive buffer level r/w 0000_0000 _0028 receive buffer base address return r/w 0000_0000 _002c control mode register r/w 0000_0000 _0030 mii mode register r/w 00f3_6400 _0034 mii command register r/w 0000_0000 _0038 mii transmit data r/w 0000_0000 _003c mii receive data r/w 0000_0000 _0040 reserved r/w 0000_0000 _0044 max, min, burst length register r/w 05dc_2e90 _0048 multicast address (most significant) r/w 0000_0000 _004c multicast address (least significant) r/w 0000_0000 _0050 mac address 0 (higher 2 bytes) r/w 0000_0000 _0054 mac address 0 (lower 4 bytes) r/w 0000_0000 _0058 mac address 1 (higher 2 bytes) r/w 0000_0000 _005c mac address 1 (lower 4 bytes) r/w 0000_0000 _0060 mac address 2 (higher 2 bytes) r/w 0000_0000 _0064 mac address 2 (lower 4 bytes) r/w 0000_0000 _0068 mac address 3 (higher 2 bytes) r/w 0000_0000 _006c mac address 3 (lower 4 bytes) r/w 0000_0000 _0070 mac address 4 (higher 2 bytes) r/w 0000_0000 _0074 mac address 4 (lower 4 bytes) r/w 0000_0000 _0078 mac address 5 (higher 2 bytes) r/w 0000_0000 _007c mac address 5 (lower 4 bytes) r/w 0000_0000 _0080 mac address 6 (higher 2 bytes) r/w 0000_0000 _0084 mac address 6 (lower 4 bytes) r/w 0000_0000 enet mac 0 controller _0088 mac address 7 (higher 2 bytes) r/w 0000_0000
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 39 _008c mac address 7 (lower 4 bytes) r/w 0000_0000 _0090 pause frame address (higher 2 bytes) r/w 0000_0180 _0094 pause frame address (lower 4 bytes) r/w c200_0001 _0098 pause frame type / op. code r/w 8808_0001 _009c pause frame delay value r/w 0000_0018 _00a0 transmit buffer base address (high priority) r/w 0000_0000 _00a4 transmit buffer length (high priority) r/w 0000_0000 _00a8 tx queue buffer level (low) r 0000_0000 _00ac tx address return (low) r 0000_0000 _00b0 tx queue buffer level (high) r 0000_0000 _00b4 tx address return (high) r 0000_0000 000b8 ? 00ffc reserved 0000_0000 1920_1000 . . . _10c8 same configuration as enet mac 0 controller enet mac 1 controller 010cc ? ffffc reserved 0000_0000 1930_0000 source pending register r/w 0000_0000 _0004 interrupt mode register w 0000_0000 _0008 interrupt enable mask register r/w ffff_ffff _000c interrupt priority control register w 0000_003f _0010 interrupt pending register r/w 0000_0000 _0014 interrupt offset register r 0000_0020 interrupt controller 00018 ? ffffc reserved prev_read_value 1940_0000 identification register r 0000_0082 _0004 interface status register (vs_in) r 0000_0000 _0008 interface control register (vs_out) r/w 0000_0000 _000c general control register r/w 0000_0001 _0010 card status change register r _0014 card status change enable register r/w 0000_0000 _0018 setup timing 0 register for bank 0 r/w 0000_000f _001c command timing 0 register for bank 0 r/w 0000_000f _0020 recovery timing 0 register for bank 0 r/w 0000_000f _0024 setup timing 1 register for bank 1 r/w 0000_000f _0028 command timing 1 register for bank 1 r/w 0000_000f pcmcia controller _002c recovery timing 1 register for bank 1 r/w 0000_000f
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 40 _0030 setup timing 2 register for bank 2 r/w 0000_000f _0034 command timing 2 register for bank 2 r/w 0000_000f _0038 recovery timing 2 register for bank 2 r/w 0000_000f _003c reserved _0040 i/o start address 0 r/w _0044 i/o end address 0 r/w n/a _0048 i/o start address 1 r/w 0000_0000 _004c i/o end address 1 r/w 0000_0000 _0050 direction control for gpio-0 (low) r/w 0000_0000 _0054 direction control for gpio-1 (high) r/w 0000_0000 _0058 output value for gpio-0 (low) r/w 0000_0000 _005c output value for gpio-1 (high) r/w 0000_0000 _0060 input value of gpi-0 (low) r/w 0000_0000 _0064 input value of gpi-1 (high) r/w 0000_0000 00068 ? 7fffc reserved 0000_0000 1948_0000 cardbus bridge command register r/w 0000_0000 _0004 cardbus bridge status register r/w 0000_0000 _0008 retry time control register r/w 0000_0000 _000c clock speed selection register r/w 0000_0000 cardbus controller 80020 ? ffffc reserved 0000_0000 1950_0000 cache control register r/w 0000_0000 cache 00004 ? ffffc reserved cache_con_reg
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 41 2.1.4. arm7tdmi core please refer to arm7tdmi manual.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 42 2.2. cache this section describes the cache system of HMS30C7110?. 2.2.1. architecture the cache of HMS30C7110? has the following characteristics. 1. 4k byte unified (data + instruction) 2. 4-way set associative 3. 64 sets 4. write back policy 5. read miss line fill up 6. 8 words depth write buffer this cache uses ?write back policy? for high performance in write accesses to cacheable area. to ensure the memory consistency between cache and main memory it supports user controllable line flush mechanism. the 8 word-depth write-buffer is used to further boost up the performance. the bit position 31 of address (most significant bit) determines whether the access is cacheable or non-cacheable. value of 0 at the 31 st address bit (0x00000000h to 0x0fffffffh) is for cacheable area, while 1 (0x10000000h to 0x1 fffffffh) is for non- cacheable area. the write buffer receives and keeps write accesses to cacheable/non-cacheable area and performs actual memory accesses when the bus is idle, program flow (dependency) forces, or user forces. accesses to cacheable/non-cacheable area originally do not go into write buffer, i.e., directly go to main memory. however, user can change this by programming user controllable registers. 2.2.2. user accessible registers (base = 0x1950_0000) there is one 32bit register to control the cache and write buffer operations (offset = 0x0). table 2.6 cache and write buffer control register address : 1950_0000 bits access default description 31:20 rw 0x0 reserved and should be set to 0. 19 rw 0x0 this bit controls burst selection.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 43 0 ? out hburst as 3?b011 (increment 4) 1 ? out hburst as 3?b001 (increment) 18 rw 0x0 this bit controls the use of cache. 0 ? cache is used for data and instruction (unified) 1 ? cache is used only for instruction (i-cache) 17 rw 0x0 this bit controls the ?bufferability? of write accesses to cacheable areas. 0 ? accesses to cacheable area are not stored into the write buffer. 1 ? accesses to cacheable area are stored into the write buffer. buffering write accesses to cacheable area can increase the performance, but in some cases it may cause problems. so it should be used with care. we recommend using the default value (non-bufferable) if user is not sure how to handle the consistency problem. 16 w 0x0 this bit flushes the current contents of the write buffer to the main memory (1 ? flush). this is recommended to be used only when the cache is off. normally it is better to read the same address of the previous write to flush the write buffer. 15:13 rw 0x0 these 3 bits control the burst length of the write buffer?s write operation. value 0-7 means 1-8 burst length. as an example, burst length 1 means that write buffer tries to write the content of the buffer as soon as at least one access comes into the buffer, and only one write access will be performed at a time. on the other hand, burst length 8 means that the write buffer will wait till there comes 8 write accesses into write buffer, and those accesses will be written to main memory in a single burst access. generally, the larger the burst length, the higher the bus efficiency. but the latency (from the time cpu writes a data to the actual writing to main memory) will increase as you use larger burst length. 12 rw 0x0 this bit controls the ?bufferability? of write accesses to non-cacheable areas. 0 ? accesses to non-cacheable area are not stored into the write buffer. 1 ? accesses to non-cacheable area are stored into the write buffer. buffering write accesses to non-cacheable area can increase the performance, but in some cases it may cause problems. so it should be
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 44 used with care. for example, write to control registers may require the ?read again? the same address to flush the write buffer. 11:6 rw 0x0 specify the set to invalid or flush (write back) ? 0 to 63 5:4 rw 0x0 specify the way to invalid or flush (write back) ? 0 to 3 3 w 0x0 line flush (write back) this bit flushes (write back) a cache line (4 words) corresponding to a specific way and a set specified in bit [5:4] and [11:6], respectively. it checks the dirty bit of a given line, write back if necessary, and then clears the valid bit. this should be activated only when the cache is off. this bit is automatically cleared to 0 as soon as the write back finishes. (actually when cache is off, it finishes immediately even before to execute the next following instruction.) this bit is used for the consistency between the cache and the main memory after the cache is off ? i.e., writes the contents of the cache if they are different (new) from those of main memory (old). 2 w 0x0 line invalidate this bit invalidates a cache line (4 words) corresponding to a specific way and a set specified in bit [5:4] and [11:6], respectively. this clears the valid bit of a given line without writing the contents of the line to main memory. this should be activated only when the cache is off. this bit is automatically cleared to 0 as soon as the invalidation finishes. (actually when cache is off, invalidation finishes immediately even before to execute the next following instruction.) 1 rw 0x0 parallel/sequential control (0 ? parallel, 1 ? sequential) this bit controls the access sequence of tag ram and data ram. parallel access of tag ram and data ram is for high performance, while sequential access is for low power operations. 0 rw 0x0 cache on/off (0 ? off, 1 ? on) this bit controls the on and off the cache. after reset, all the valid bits of cache are cleared to 0. so there are no required procedures to turn on the cache in the initial state. however, there should be some caution when turn off the cache since even if the cache is turned off, all the operations of the cache except the line fill is performed as usual. for example, a
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 45 cache read hit can occur, and the corresponding data/inst from the cache goes to cpu. similarly, a write hit can occur, and the corresponding data write to cache follows. so, after turn off the cache, user should flush all the cache lines (preferably using codes in a non-cacheable area) if he/she wants to get(put) data/inst from(to) main memory directly.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 46 2.3. clock/watchdog timer the HMS30C7110? integrates a clock module, which is composed of the clock generator, the reset de-bouncing circuit, and watchdog timer (wdt). the clock generator provides the system clock. the main pll multiplies the incoming external crystal clock input by 7(default). assuming 10 mhz external clock is used and 70mhz of the cpu speed is intended, the register setting is to be ?multiplying by 7?. an internal register also provides a method to determine the ratio between cpu clock and bus clock. it can be either 1:1 or 2:1. to run cpu with maximum performance, set the pll output frequency to 70mhz and set the ratio to 1:1, then cpu runs in 70mhz and all others run at 70 mhz. watchdog timer generates the reset signal internally when the timer reaches the end value. so, the controlling software must reload the preset value to the timer before the timer expires during normal operation. complete descriptions of these registers are given in the register section. 2.3.1. block diagram the clock module consists of several blocks such as a register file, a reset de-bouncer, a clock generator, and a watchdog timer. reset debounce register file ( slave ) dll clock generator hresetn reset_in system clock peripheral bus figure 2.1 block diagram of clock module
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 47 2.3.2. user accessible registers (base = 0x1830_0000) this section describes the registers in the clock module. the address value on the table shows the relative address in hexadecimal. the width describes the number of bits in the register. the access field specifies the valid access type for the register, where ?rw? stands for read and writes access, and ?ro? for read only access, respectively. ?c? following ?rw? or ?ro? means the corresponding bit is cleared after writing ?1? in the matching position. table 2.7 registers for pll & watchdog timer name address width access description pll enable 0x00 32 rw enable for pll clocks wdt control 0x04 32 rw control for watch dog timer wdt interval 0x08 32 rw time interval for watch dog timer main pll control 0x0c 32 rw control for main pll pll reset 0x10 32 r status of pll 2.3.2.1. pll enable this register is used to select internal three clocks between external low frequency clock and internal pll output clock. table 2.8 pll control address : 1830_0000 bits access default description 31:4 0x00 reserved 3 rw 0x1 bus clock ratio vs. cpu clock. sclk is from the bus clock. 0 = bus clock is divided by 2 from cpu clock 1 = bus clock is delibered directly from cpu clock 2:1 0x0 reserved
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 48 0 rw 0x0 main pll enable when this bit is set to logic 1, internal cpu and system clock is made from pll output. if this is set to logic 0, the internal cpu and system clock is made directly from external clock pin. the system clock is same to the bus clock or system bus clock. 2.3.2.2. watch dog timer (wdt) control the watch dog control register selects the operation mode of watchdog timer. table 2.9 watch dog timer control address : 1830_0004 bits access default description 31:5 0x00 reserved 4 rw 0x0 enable 0 = watch dog timer disable 1 = watch dog timer enable 3:2 0x0 reserved 1: 0 rw 0x0 pre-scaler 00 = system bus clock 01 = system bus clock/ 4 10 = system bus clock/ 8 11 = system bus clock/ 256 2.3.2.3. watch dog timer (wdt) interval this register contains the watchdog timer interval value. the input clock is the output clock of the pre-scaler described in watch dog timer (wdt) control table 2.10 watch dog timer interval address : 1830_0008
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 49 bits access default description 31: 0 rw 0x0 interval (write) or current wdt counter value (read) this 32-bit field contains the interval value that will be loaded to down counter periodically. 2.3.2.4. main pll control the main pll control register selects the operating mode of pll. refer to h25pl12s data sheet for more detailed information about pll control. table 2.11 main pll control address : 1830_000c bits access default description 31:29 rw 0x5 lfm : loop filter mode selector. ** use default value for normal operation, set 0x7 only if external filter logic is used for lower frequency (< 150khz). 28:15 rw 0x0c m : feedback divisor 14:7 rw 0x1 n : reference divisor vco clock frequency will be determined with m and n based on following equation: f vco = f ref x (m+2) / (n+1) as a default, f vco = 10mhz x (12+2) / (1+1) = 70mhz. 6:5 rw 0x0 p : post divisor this field defines division factor after vco. for example, if p=1 and vco output frequency is 20mhz, final pll output frequency will be 10mhz (f pll = f vco / (p+1) ) 4 rw 0x0 pd : pll power down mode except vco if set to ?1?, pll will not generate clock though vco is still working. 3:2 rw 0x1 vc : vco range control vector this field defines operation range of vco. 00 : 40mhz ? 100mhz 01 : 60mhz ? 120mhz 10 : 80mhz ? 140mhz
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 50 11 : 100mhz ? 160mhz 1 rw 0x0 vcoinit : vco initialize signal during power-up sequence, vcoinit is recommended to be activated for more than 100ns just after deactivation of the vcopd signal. 0 rw 0x0 vcopd : vco power down mode if set to ?1?, pll will not generate clock and vco will stop. fck = fref (m+2) / (n + 1) 2.3.2.5. pll status this register controls software reset of pll and some of control signals of pll module and indicates pll locking status. table 2.12 pll status address : 1830_0010 bits access default description 31 rw 0x0 bypass, pll bypass mode ?active high? 30 rw 0x0 cnttest, pll counter toggle test ?active high? 29 rw 0x0 lfo, pll external loop filter port ? analog? 28:25 rw 0xa icp, pll charge pump bias current control vector 24 rw 0x0 tdm, pll digital part test mode ?active high? 23:22 rw 0x0 tpdud, pll charge pump test mode (normal mode ?00?) 21:5 0x0 reserved 4 rw 0x0 pll software reset ?active high? 3:1 0x0 reserved 0 r 0x0 main pll locking end: high active refer magnachip pll user guide
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 51
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 52 2.4. memory controller (flash/rom) the HMS30C7110? has integrated external bus controller that supports 8-bit/16-bit/32-bit data bus width. the space is divided into 3 static memory (flash/rom) banks. each bank has fixed size of 4mb. the operating clock of external bus controller is the internal system bus clock. the bus timing exclusively depends on the register programming. the external bus controller is fully configurable through a set of control register. complete descriptions of these registers are given in the register section. the twenty-two address lines, ra [21:0], allow HMS30C7110? to support up to 1m 32 bit, 2mx16 bit, or 4mx8 bit space. three nrcs lines make three times bigger space. each block can be configured independently for the bus style, the wait enable, the shaping of bus control signal. 2.4.1. block diagram the external bus controller of HMS30C7110? consists of several blocks such as main state machine, register file, data-path, signal generator and address generator. commands fed via system bus are interpreted in the main state machine and the main state machine generates control signals to all of the signal generation blocks (address generator, signal generator and data-path) using the state signal. the data-path block makes dataout signal using hwdata and makes hrdata using datain signal according to state signal. in write operation, the data-path block asserts the direction signal to enable output path of data pads. the signal generator makes nrcs, noe, and nwe.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 53 configruation registers signals generator address control data path main control logic nrcs0-2 noe nwe data addr pcmcia control ncs0,1 niord niowr ready/nirq nreg/dack nstschg iois16/ndreq system bus int figure 2.2 block diagram of external controller 2.4.2. user accessible registers (base = 0x1900_0000) this section describes the bit assignment of the configuration registers of the rom controller. the address field indicates a relative address in hexadecim al. width specifies the number of bits in the register and access specifies the valid access types of the register. where rw stands for read access and write access, ?ro? for read only access. a ?c? appended to ?rw? or ?ro?, indicates that some or all of the bits can be cleared after writing ?1? in corresponding bit.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 54 table 2.13 registers for rom controller name address width access description configuration 0 0x00 32 rw timing configuration of bank 0 configuration 1 0x04 32 rw timing configuration of bank 1 configuration 2 0x08 32 rw timing configuration of bank 2 2.4.2.1. configuration 0~3 these registers include timing information for all banks. table 2.14 configuration registers bit definition address : 1900_0000, 1900_0004, 1900_0008 bits access default description 31:30 0 reserved 29:28 rw 0 bus mode 00 = a/d non-mux style 01 = a/d mux intel style 10 = a/d mux, motorola style 11 = reserved 27 rw 0 wait enable this 1 bit field accepts/denies the external wait (gpio2/wait) signal pin expending the access time. 0 = disable 1 = enable 26 rw 0 this bit selects the active level of wait signal, which would be connected to gpio2/wait on pin 206. each setting for each configuration register affect only on assigned address range. 0 = active low input 1 = active high input 25:24 rw 0x3 data bus width 00 = 8 bit wide bus 01 = 16 bit wide bus
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 55 10 = 32 bit wide bus 11 = reserved external pull-up/downs on addr 19 and addr18 applies for booting configuration. boot program should be appeared on nrcs0. can be changed by configuration 0 afterward. 23:20 rw 0x3 0xf astb time this 4-bit field selects the pulse width of the address strobe signal when a/d mux bus mode is on. 19:16 rw 0x3 0xf addr time this 4-bit field selects the address phase interval when a/d mux bus mode is on. 15:12 rw 0x0 0xf recovery time this 4-bit field selects the recovery time delay, this value guarantee the interval from the end of one chip select assertion to the start of another chip select assertion. 11: 8 rw 0x0 0xf setup time this 4-bit field selects the setup time duration, this value guarantees the interval from chip select asserti on to read enable or write enable assertion. 7: 4 rw 0xf access time this 4-bit field selects the access time and this value guarantees the asserted pulse width of read enable or write enable signal. 3: 0 rw 0xf hold time this 4-bit field selects the hold time duration and this value guarantees the interval from read enable or write enable de-assertion to chip select de-assertion. note: the first value in the box es with two defaults values sho w the default for rom bank0 and the second value for the remaining two banks, ban k1 and bank2. note: all units are based on the main clock period.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 56 2.4.3. timing diagram 2.4.3.1. read access clk ra nrcs nwe noe data address data 0 setup a c c e s s + 1 hold figure 2.3 read cycle timing (setup = 4, access = 6, hold = 4) 2.4.3.2. write access clk ra nrcs nwe noe data address data 0 setup a c c e s s + 1 hold figure 2.4 write timing (setup = 4, access = 6, hold = 4)
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 57 2.5. memory controller (sdram) the HMS30C7110? integrates a sdram controlle r (sdramc) that supports a 32-bit sdram array. edo or fpm type dram is not supported. the operating clock is directly related to the internal system bus speed. when the system bus clock runs at 70mhz, the sdramc runs at 70mhz. when the system bus clock runs at 35mhz, the sdramc runs at 35mhz. the system clock can be selected by pll output clock or half of pll output clock. the sdramc is fully configurable through a set of control register. complete descriptions of these registers are given in the register section. the operating clock of sdramc is shown on sclk. note: sdram space works either in 32-bit wide or in 16-bit wide. so, any design using the sdram space as program memory space, it can be either 32-bit wide memory structure or 16-bit wide structure. being used as data memory space, sdram may be connected to 8-bit wide data bus sacrificing the address corr esponding to unconnected data bus. the thirteen multiplexed address lines, ma[12:0], and two bank select signals, a13 and a14, allow the HMS30C7110? to support 1m, 2m, 4m, 8m, 16m and 32m 32 bit arrays or 1m, 2m, 4m, 8m, 16m, 32m and 64m 16 bit arrays. both symmetric (number of row addresses and number of column addresses are same) and asymmetric addressing (number of row addresses and number of column addresses are different) is supported. the HMS30C7110? has one nscs pin. the maximum block size is 128mbytes. for write operations of less than word in size, the HMS30C7110? supports byte-wise write. the HMS30C7110? provides refresh functionality with programmable rate (normally sdram refresh rate is 1 / 64ms). 2.5.1. block diagram the sdram controller of HMS30C7110? consists of several blocks such as main state machine, register file, refresh block, data-path, signal generator and address generator. commands come in via system bus will be interpreted in the main state machine and the main state machine controls all of the signal generation blocks (address generator, signal generator and data-
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 58 path) using state information of main state machine. the refresh block makes bus request signal to system bus arbiter to start refresh operation and when the system bus arbiter gives bus grant signal to sdram controller, the main control logic detects this signal and makes refresh command to signal generator. the data-path block makes dataout signal using system write data bus and makes system read data bus using datain signal according to state signal. in write operation, the data-path block asserts the direction signal to enable output path of data pads. configruation registers signals generator address control data path main control logic nras ncas data addr system bus refresh controller dqm nswe nscs figure 2.5 block diagram of sdram controller 2.5.2. user accessible registers (base = 0x1908_0000) this section describes all base, control and st atus register inside the sdram controller. the address field indicates a relative address in hexadecimal. width specifies the number of bits in the register and access specifies the valid access types that register. where ?rw? stands for read and
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 59 write access, ?ro? for read only access. a ?c? appended to ?rw? or ?ro?, indicates that some or all of the bits can be cleared after a write ?1? in corresponding bit. table 2.15 registers for sdram controller name address width access description configuration 0x00 32 rw sdram configuration reserved 0x04 32 reserved reserved 0x08 32 reserved reserved 0x0c 32 reserved timing 0x10 32 rw sdram timing parameters refresh interval 0x14 32 rw refresh interval value & mclk timing init control 0x18 32 rw initialize start register address map 0x1c 32 rw select address area (flash or sdram) 2.5.2.1. configuration these registers include the information of memory size of each bank. table 2.16 configuration register address : 1908_0000 bits access default description 31:22 0x0 reserved 21:20 rw 0x0 row width 00 = 10-bit row width 01 = 11-bit row width 10 = 12-bit row width 11 = 13-bit row width 19:18 0x0 reserved 17:16 rw 0x0 column width 00 = 8-bit column width 01 = 9-bit column width
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 60 10 = 10-bit column width 11 = reserved 15:14 0x0 reserved 13: 8 rw 0x0 start address (reserved for future usage) 7: 6 0x0 reserved 5: 0 rw 0x3f end address (reserved for future usage) 2.5.2.2. timing this register includes the timing information for all banks. table 2.17 timing register address : 1908_0010 bits access default description 31 wo 0x0 nop when writing 1 at this bit, it will make nop command to sdram 30:28 rw 0x7 tmode (mode register set to active delay) this 3-bit field specifies the number of cycles guaranteed between mode register set command at the end of the initialization sequence and the first activate command. 27 0x0 reserved. 26:24 rw 0x7 dpl (write to pre-charge delay) this 3-bit field specifies the number of cycles guaranteed between write command and a pre-charge command. 23 0x0 reserved. 22:20 rw 0x7 rcd (ras to cas delay) this 3-bit field specifies the number of cycles between ras and cas. 19 0x0 reserved 18:16 rw 0x7 rp (row pre-charge time) this 3-bit field specifies the number of cycles needed for the pre-charge command. a rp value of zero results in a ras pre-charge of two clocks, as if rp was selected to 1.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 61 15:12 rw 0xf ras (row active time) this 4-bit field specifies the number of cycles guaranteed between an activate command and a pre-charge command. 11: 8 rw 0xf rc (row cycle time) this 4-bit field specifies the number of cycles for a refresh command. it also specifies the number of cycles between bank activation commands to the same bank. 7: 6 0x0 reserved 5: 4 rw 0x7 cl (cas latency) this value is used to program the sdram devices during the initialization sequence, and internally by the sdram controller. 0 = 1 clock 1 = 2 clocks 2 = 3 clocks 3 = reserved 3: 2 0x0 reserved 0 rw 0x1 row hit enable this value is used to enable the checking of the row address from internal logic matched with row address of destination sdram. it may cause one or two clock delay in accessing sdram but will make sure that correct operation will be happening. 0 : do not check whether row address is hit or not. 1 : check whether row address is hit or not. 2.5.2.3. refresh interval this register includes refresh interval value and mclk tuning control reginter. table 2.18 refresh interval address : 1908_0014 bits access default description 31:29 0x0 reserved.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 62 28 0x1 clock select for sdram read. 1 : clock source = sclk output 0 : clock source = mclk input 27:24 0x3 delay for sdram read clock (0-15ns). 23:21 0x0 reserved. 20 0x0 clock select for sdram write. 1 : clock source = sclk output 0 : clock source = mclk input 19:16 0x3 delay for sdram write clock (0-15ns). 15:13 0x0 reserved 12: 0 0x0 refresh interval this 13-bit field is used to enable refresh and set the refresh period. when set to zero, refresh cycles are disabled. when set to non-zero, refresh cycles are enabled, and are requested internally based on this programmed value. rp and rc control the timing waveform of refresh cycle. this field is set to zero on the hard reset, so refreshes are disabled after a hard reset. this field is a one-based number, and is programmed in clk period.(1/clk) t refint = (refint + 1) /clk 2.5.2.4. init control this register includes init bit. table 2.19 init control register address : 1908_0018 bits access default description 31:1 reserved. 0 wo 0 init this bit when set invokes an sdram power up initialization sequence. all other fields in this register must be programmed with valid values before or at the same time init is set. once the initialization sequence is
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 63 complete, hardware clears this bit, so it may be polled by software to determine when the sdram(s) is (are) available for use. 2.5.2.5. address map control this register includes data bus width selection/memory re-map bits. table 2.20 address control register address : 1908_001c bits access default description 31:2 reserved. 1 rw 0 32/16bit data bus width selection 0 = 32 bit 1 = 16 bit 0 rw 0 sdram_remap 0 = address 0x0000_0000 is located at flash memory area (sdram will be 0x1000_0000) 1 = address 0x0000_0000 is located at sdram area 2.5.3. timing diagram 2.5.3.1. read/write access
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 64 clk ma nras ncas nwe data col row pre col col col row col col col col pre d0 d1 d3 d2 d0 d1 d3 d2 rc + 1 ras + 1 r c d + 1 rp + 1 dpl +1 cl figure 2.6 read/write cycle 2.5.3.2. refresh access clk ma nras ncas nwe data pre row col col col col pre d0 d1 d3 d2 rc + 1 rcd + 1 rp + 1 cl figure 2.7 refresh cycle
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 65 2.5.3.3. initialization table 2.21 initialization sequence sequence sdram requirement comments 1 apply power and start clock mclk operates during reset period 2 maintain stable power and clock for at least 1 ms power on reset normally takes longer than 1 ms 3 nop command (optional) software asserts nop command using command register 4 waiting for min 200 us software waits for 200 us using for-loop or while-loop 5 software sets valid values in timing registers 6 software sets the refresh interval 7 pre-charge all banks of all blocks software sets the init bit of command register 8 perform 20 times refresh cycles 9 program sdram mode register 10 polling the init bit and if init bit is cleared, then initialization is finish
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 66 clk ma ncs nras ncas nwe mod row pre r c + 1 rp + 1 init tmode 200 us nop 1st cbr 20th cbr figure 2.8 initialization timing
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 67 2.6. ethernet mac HMS30C7110? provides an ethernet media access co ntroller (mac) that operates at either 10 mbps or 100 mbps in half-duplex or full-duplex mode. in half-duplex mode, the controller supports the ieee 802.3 carrier sense multiple access with collision detection (csma/cd) protocol. it supports the ieee 802.3 mac control layer, i ncluding the pause operation for flow control for full- duplex mode. the ethernet mac layer supports both media independent interface (mii) / reduced mii (rmii) and 7-wire interface. the host side supports dma interface to the system bus. the mac layer itself consists of the receive and the transmit blocks, a flow control block, multiple network address storage, and a number of commands, and status registers. the transmit and receive clocks will be supplied either from physical layer devices or external clock sources. they are either 2.5mhz at the 10 mbps or 25mhz at the 100 mbps. the external clock for rmii is 50mhz regardless of data rate. the mii conforms to the iso/iec 802-3 standard for a media-independent layer which separates physical layer issues form the mac layer. it also provides mac address filtering, which is to drop frames with designated mac addresses while all ot her frames are received. 2.6.1. block diagram HMS30C7110? ethernet mac module consists of several sub-modules such as mii management, physical layer interface, receive, transmit, control, and host interface. frames come in via either 7-wire interface (bit-wide) or mii (nibble-wide) / rmii (di-bit-wide) and receive module will detect start of frame. once it verifies a valid sync pattern, a frame will be stored in the mac receive fifo starting from the destination address field. the state machine also monitors total number of bytes in a frame by looking at data length field. when the level of the mac receive fifo is more than the threshold value, the stored frame will be read to the sy stem receive fifo at system clock speed. another state machine running at the system clock speed will detect destination address, data length, and crc for validity of the frame. the destination address is sent to address compare block for comparison with the stored mac addresses. if the destination address is found to be a valid address, then the frame will be written into the system receive fifo. if the received address is a multicast
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 68 address, then crc will be calculated over 48-bit destination address, and 5 most significant bits are used to locate one of 64 bits of the multicast address register. if the bit to be pointed by the 5 most significant bits is set, then the frame will be received. with sufficient number of bytes held in the system receive fifo, the dma engine will start transfer the stored frame to the system memory space that is pre-programmed by the cpu. an interrupt will be asserted to notify that a frame transfer is completed and the cpu should write the start address of the next buffer for the next incoming frame. in transmit operation, the cpu prepares a frame and notify the mac that a frame is ready to transfer. the mac dma engine moves the frame from the system memory to system transmit fifo. when the state machine detects there is a frame being stored in the system transmit fifo and that carrier sense is not detected, the frame will be transferred. pad byte (0x00) may be inserted if required, and crc will be appended at the end of the frame. preamble will be added before the frame, jam signaling will be asserted when collis ion occurs. the data stream will be either serialized for the 7-wire interface or converted to nibbles/bi-bits for mii/rmii. d m a - s y s t e m b u s frame mux sys tx fifo fifo ctrl pad insert / mux p h y i / f - (r) m i i sfd check mac rx fifo fifo ctrl sys rx fifo config status crc crc addr timer figure 2.9 block diagram of ethernet mac
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 69 below table show the phy interface i/o signals port width direction description mtxclk 1 i transmit nibble or symbol clock. the phy provides the mtxclk signal. it operates at the frequency of 25mhz (100mbps) or 2.5mhz (10mbps). the clock is used as a timing reference for the transfer of mtxd[3:0], mtxen, and mtxerr. mtxd[3:0] 4 o transmit data nibble. signals are the transmit data nibble. they are synchronized to the rising edge of mtxclk. when mtxen is asserted, phy accepts the mtxd. if 7-wire interface is selected, mtxd[0] will carry data bits, all others will be tri-stated. mtxen 1 o transmit enable. when asserted, signal indicates to the phy that the data mtxd[3:0] is valid and the transmission can start. then transmission starts with the first nibble of the preamble. signal remains asserted until all nibbles to be transmitted are presented to the phy. it is deasserted prior to the first mtxclk following the final nibble of a frame. mtxerr 1 o transmit coding error. when asserted for on e mtxclk clock period while mtxen is also asserted, it causes the phy to transmit one or more symbols that are not part of the valid data or delimiter set somewhere in the frame being transmitted to indicate that there has been a transmit coding error. mrxclk 1 i receive nibble or symbol clock. the phy provides the mtxclk signal. it operates at the frequency of 25mhz (100mbps) or 2.5mhz (10mbps). the clock is used as a timing reference for the reception of mrxd[3:0], mrxdv and mrxerr. mrxdv 1 i receive data valid. the phy asserts this signal to indicate to the rx mac that it is presenting the valid nibbles on the mrxd[3:0] signals. signal is asserted synchronously to the mrxclk. mrxdv is asserted from the first recovered nibble of the frame to the final recovered nibble. it is then deasserted
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 70 prior to the first mrxclk that follows the final nibble. mrxd[3:0] 4 i receive data nibble. signals are the receive data nibble. they are synchronized to the rising edge of mrxclk. when mrxdv is asserted, the phy sends a data nibble to the rx mac. for a correctly interpreted frame, seven bytes of a preamble and a completely formed sfd must be passed across the interface. if 7-wire interface is selected, mrxd[0] will carry data bits, all others will be unused. mrxerr 1 i receive error. phy asserts this signal to indicate to the rx mac that a media error was detected during the transmission of the current frame. mrxerr is synchronous to the mrxclk and is asserted for one or more mrxclk clock periods and then deasserted. mcoll 1 i collision detected. the phy asynchronously asserts the collision signal mcoll after the collision is detected on the media. when deasserted, no collision is detected on the media. mcrs 1 i carrier sense. the phy asynchronously asserts the carrier sense mcrs signal after the medium is detected in a non-idle state. when deasserted, signal indicates that the media is in the idle state (and the transmission can start). mdc 1 i management data clock. clock for the mdio serial data channel. mdio 1 i/o management data input/output. bi-directional serial data channel for phy/sta communication. phy interface signals 2.6.2. user accessible registers (base = 0x1920_0000) this section describes registers inside the ethernet mac. the address field in the following table indicates an address offset in hexadecimal from ethernet base address defined in the cpu section. width specifies the number of bits in the register and access specifies the valid access types of the register. where ?rw? stands for read and write access, ?ro? for read only access. a ?c? indicates
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 71 that some or all of the bits are auto cleared. base address of ethernet mac 1 is 0x1920_1000. table 2.22 registers for ethernet mac name address width access description mac_mode 0x00 32 rw mac mode register int_src 0x04 32 rw interrupt source register int_enable 0x08 32 rw interrupt enable register if_gap 0x0c 32 rw inter-frame gap register coll_cfg 0x10 32 rw collision control register tx_baddr 0x14 32 rw transmit buffer base address tx_length 0x18 32 rw transmit buffer length rx_baddr 0x1c 32 rw receive buffer base address rx_bstat 0x20 32 ro receive buffer status rx_buflvl 0x24 32 ro address/status buffer level rx_addr_back 0x28 32 ro receive buffer base address return ctrl_mode 0x2c 32 rwc control mode register mii_mode 0x30 32 rw mii mode register mii_cmd 0x34 32 rwc mii command register mii_txdata 0x38 32 rw mii transmit data mii_rxdata 0x3c 32 rw mii receive data reserved 0x40 32 reserved length 0x44 32 rw max, min, burst length register mcast_addr_0 0x48 32 rw multicast address (most significant) mcast_addr_1 0x4c 32 rw multicast address (least significant) mac_addr_00 0x50 32 rw mac address 0 (most significant 2 bytes) mac_addr_01 0x54 32 rw mac address 0 (least significant 4 bytes) mac_addr_10 0x58 32 rw mac address 1 (most significant 2 bytes) mac_addr_11 0x5c 32 rw mac address 1 (least significant 4 bytes) mac_addr_20 0x60 32 rw mac address 2 (most significant 2 bytes) mac_addr_21 0x64 32 rw mac address 2 (least significant 4 bytes) mac_addr_30 0x68 32 rw mac address 3 (most significant 2 bytes)
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 72 mac_addr_31 0x6c 32 rw mac address 3 (least significant 4 bytes) mac_addr_40 0x70 32 rw mac address 4 (most significant 2 bytes) mac_addr_41 0x74 32 rw mac address 4 (least significant 4 bytes) mac_addr_50 0x78 32 rw mac address 5 (most significant 2 bytes) mac_addr_51 0x7c 32 rw mac address 5 (least significant 4 bytes) mac_addr_60 0x80 32 rw mac address 6 (most significant 2 bytes) mac_addr_61 0x84 32 rw mac address 6 (least significant 4 bytes) mac_addr_70 0x88 32 rw mac address 7 (most significant 2 bytes) mac_addr_71 0x8c 32 rw mac address 7 (least significant 4 bytes) p_frm_addr_0 0x90 32 rw pause frame address (most significant 2 bytes) p_frm_addr_1 0x94 32 rw pause frame address (least significant 4 bytes) p_frm_id 0x98 32 rw pause frame type / op. code p_frm_value 0x9c 32 rw pause frame delay value h_tx_baddr 0xa0 32 rw high priority queue tx address h_tx_length 0xa4 32 rw high priority queue tx length tx_buf_lvl_l 0xa8 32 ro tx queue buffer level tx_addr_bk_l 0xac 32 ro tx address return tx_buf_lvl_h 0xb0 32 ro tx high priority queue buffer level tx_addr_bk_h 0xb4 32 ro tx high pr iority queue address back buffer level rx_timer 0xb8 32 rw rx timer register rx_level 0xbc 32 rw rx level register tx_timer 0xc0 32 rw tx timer register tx_level_h 0xc4 32 rw tx level register high tx_level_l 0xc8 32 ro tx level register low 2.6.2.1. mac_mode (offset = 0x00) this register defines general operation mode of the ethernet mac.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 73 table 2.23 mac mode register bit definition mac0 address : 1920_0000 mac1 address : 1920_1000 bits access default description 31 rw 0 unicast_enable 0 = disable receiving unicast frames 1 = enable receiving unicast frames 30 rw 0 multicast_enable 0 = disable receiving multicast frames 1 = enable receiving multicast frames 29 rw 0 broadcast_enable 0 = disable receiving broadcast frames 1 = enable receiving broadcast frames 28 rw 0 receive_all_enable 0 = frames will be received based on bits [31:29]. 1 = enable receiving all frames. when ?1?, if any mac address is set to be valid, the frame with valid mac address will be dropped (see valid bit of mac address registers). 27:19 0 reserved 18 rw 0 tx error signaling 0 = low output at tx_er pin for error signaling 1 = high output at tx_er pin for error signaling 17 rw 1 tx data valid polarity 0 = active low data valid output to phy 1 = active high data valid output to phy 16 rw 0 tx_en 0 = disable tx after the current frame is transmitted 1 = enable tx 15:11 0 reserved 10 rw 1 rx error polarity 0 = active low error output to phy 1 = active high error output to phy
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 74 9 rw 1 rx data valid polarity 0 = active low data valid input from phy 1 = active high data valid input from phy 8 rw 0 rx_en 0 = receive disabled after the current packet is received 1 = receive enabled 7 rw 0 speed 1 = 100mbps 0 = 10mbps 6 rw 0 rmii enable 1 = rmii mode regardless of bit[1] 0 = mii or 7-wire mode according to bit[1] 5 rw 1 collision polarity 0 = active low collision input from phy 1 = active high collision input from phy 4 rw 1 carrier sense polarity 0 = active low carrier sense input from phy 1 = active high carrier sense input from phy 3 rw 0 loop-back mode 0 = normal operation 1 = enable mac loop-back 2 rw 0 full / half duplex mode 0 = half duplex mode 1 = full duplex mode 1 rw 0 interface select 0 = 7-wire 1 = mii 0 rwc 0 reset mac 0 = normal operation 1 = reset active (auto-clear after reset is done)
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 75 2.6.2.2. int_src (offset = 0x04) the ethernet mac provides 30 interrupt sources. table 2.24 interrupt source bit definition mac0 address : 1920_0004 mac1 address : 1920_1004 bits access default description (write ?1? to clear each bit) 31 rw 0 1 = mii phy interrupt 30 rw 0 1 = mii scan interrupt 29 rw 0 1 = tx error at phy 28 rw 0 1 = rx error at phy 27 rw 0 1 = tx address return buffer overflow. 26 rw 0 1 = tx address return buffer underflow 25 rw 0 1 = collision detected 24 rw 0 1 = carrier sense detected 23 0 reserved. 22 rw 0 1 = tx complete (high priority queue) 21 rw 0 1 = late collision detected 20 rw 0 1 = tx completed (low priority queue) 19 rw 0 1 = sys tx fifo overflow 18 rw 0 1 = sys tx fifo underflow 17 rw 0 1 = mac tx fifo overflow 16 rw 0 1 = mac tx fifo underflow 15 rw 0 1 = tx length buffer overflow (low priority queue) 14 rw 0 1 = tx length buffer underflow (low priority queue) 13 rw 0 1 = tx address buffer overflow (low priority queue) 12 rw 0 1 = tx address buffer underflow (low priority queue) 11 rw 0 1 = rx status buffer overflow 10 rw 0 1 = rx status buffer underflow 9 rw 0 1 = rx address buffer overflow 8 rw 0 1 = rx address buffer underflow
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 76 7 0 reserved 6 rw 0 1 = rx frame cut due to bus busy & excessive incoming frames 5 rw 0 1 = rx frame dropped due to no buffer assigned. 4 rw 0 1 = rx completed. 3 rw 0 1 = sys rx fifo overflow 2 rw 0 1 = sys rx fifo underflow 1 rw 0 1 = mac rx fifo overflow 0 rw 0 1 = mac rx fifo underflow 2.6.2.3. int_enable (offset = 0x08) each bit of this register can be set to enable corre sponding interrupt source. writing ?0? disables the source from generating interrupt. table 2.25 interrupt enable bit definition mac0 address : 1920_0008 mac1 address : 1920_1008 bits access default description 31 rw 0 mii phy 0 = interrupt disabled 1 = interrupt enabled this bit will be set whenever phy device sends an interrupt 30 rw 0 mii scan 0 = interrupt disabled 1 = interrupt enabled this bit will be set when single read is completed in scan mode. refer to mii_cmd register (offset = 0x34). 29 rw 0 tx error occurred at phy 0 = interrupt disabled 1 = interrupt enabled 28 rw 0 rx error occurred at phy
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 77 0 = interrupt disabled 1 = interrupt enabled. 27 rw 0 tx address return buffer overflow. 0 = interrupt disabled 1 = interrupt enabled. 26 rw 0 tx address return buffer underflow 0 = interrupt disabled 1 = interrupt enabled. 25 rw 0 collision detected 0 = interrupt disabled 1 = interrupt enabled 24 rw 0 carrier sense detected 0 = interrupt disabled 1 = interrupt enabled 23 0 reserved. 22 rw 0 tx complete (high priority queue) 0 = interrupt disabled 1 = interrupt enabled 21 rw 0 late collision detected (tx frame dropped) 0 = interrupt disabled 1 = interrupt enabled 20 rw 0 tx completed 0 = interrupt disabled 1 = interrupt enabled 19 rw 0 sys tx fifo overflow. 0 = interrupt disabled 1 = interrupt enabled 18 rw 0 sys tx fifo underflow. 0 = interrupt disabled 1 = interrupt enabled 17 rw 0 mac tx fifo overflow 0 = interrupt disabled 1 = interrupt enabled
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 78 16 rw 0 mac tx fifo underflow. 0 = interrupt disabled 1 = interrupt enabled 15 rw 0 tx length buffer overflow (low priority queue) 0 = interrupt disabled 1 = interrupt enabled 14 rw 0 tx length buffer underflow (low priority queue) 0 = interrupt disabled 1 = interrupt enabled 13 rw 0 tx address buffer overflow (low priority queue) 0 = interrupt disabled 1 = interrupt enabled 12 rw 0 tx address buffer underflow (low priority queue) 0 = interrupt disabled 1 = interrupt enabled 11 rw 0 receive status buffer overflow 0 = interrupt disabled 1 = interrupt enabled 10 rw 0 receive status buffer underflow 0 = interrupt disabled 1 = interrupt enabled 9 rw 0 receive address buffer overflow 0 = interrupt disabled 1 = interrupt enabled 8 rw 0 receive address buffer underflow 0 = interrupt disabled 1 = interrupt enabled 7 0 reserved 6 rw 0 rx frame cut due to bus busy & excessive incoming frames 0 = interrupt disabled 1 = interrupt enabled 5 rw 0 received frame is dropped due to no buffer. 0 = interrupt disabled
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 79 1 = interrupt enabled 4 rw 0 rx completed 0 = interrupt disabled 1 = interrupt enabled 3 rw 0 sys rx fifo overflow. 0 = interrupt disabled 1 = interrupt enabled 2 rw 0 sys rx fifo underflow. 0 = interrupt disabled 1 = interrupt enabled 1 rw 0 mac rx fifo overflow 0 = interrupt disabled 1 = interrupt enabled 0 rw 0 mac rx fifo underflow. 0 = interrupt disabled 1 = interrupt enabled 2.6.2.4. if_gap (offset = 0x0c) this register defines a gap time between two back-to-back frames. table 2.26 inter-frame gap register mac0 address : 1920_000c mac1 address : 1920_100c bits access default description 31:7 0 reserved 6:0 rw 0x18 back to back inter packet gap the recommended value is 0x0c (24 ? 12 = 12) for mii, 0x54 (96 ? 12 = 84) for 7-wire interface, which equals to 0.96us (100mbps) or 9.6us (10mbps).
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 80 2.6.2.5. coll_cfg (offset = 0x10) this register defines collision related parameters. table 2.27 collision configuration definition mac0 address : 1920_0010 mac1 address : 1920_1010 bits access default description 31:16 rw 0x000f maximum retry this field specifies the maximum number of consequential retransmission attempts after the co llision is detected. when the maximum number is reached the mac reports an error and tops transmitting the current packet. accordi ng to the ethernet standard, the maximum retry default value is set to 0xf (15 in decimal) 15:8 rw 0x20 write allowance define the margin in system fifo to prevent overflow. 7:0 rw 0x10 collision window define the number of data from the start of transmission until collision is detected. if collision is detected before the number of data is reached this value, it will be considered as retry able collision. 2.6.2.6. tx_baddr (offset = 0x14) the start address of outgoing frame is written in this register. writing to tx_baddr and tx_length will initiate transmission process. table 2.28 transmit buffer address mac0 address : 1920_0014 mac1 address : 1920_1014
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 81 bits access default description 31:0 rw 0x0 transmit buffer start address 2.6.2.7. tx_length (offset = 0x18) the total frame length (starting from destination address to the end of frame, excluding crc field) should be written to this register. table 2.29 transmit buffer length mac0 address : 1920_0018 mac1 address : 1920_1018 bits access default description 31:16 rw 0x00 reserved 15:0 rw 0x00 transmit buffer length in bytes 2.6.2.8. rx_baddr (offset = 0x1c) the starting address of rx buffer to store incoming frame is written to this register. rx_baddr can hold 15 entries of the start address of rx buffer. the number of entries not taken for rx processing can be read from bits[10:8] of rx_buflvl (offset = 0x24). not assigning a buffer address in time will result in an interrupt (if enabl ed) with int_src bit[5] and the frame will be dropped. table 2.30 receive buffer address mac0 address : 1920_001c mac1 address : 1920_101c bits access default description 31:0 rw 0x00 receive buffer start address
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 82 2.6.2.9. rx_bstat (offset = 0x20) this address can hold 32 entries of the status of rx frames. the number of status of frames not read can be obtained from bits[5:0] of rx_buflvl (offset = 0x24). table 2.31 receive frame status mac0 address : 1920_0020 mac1 address : 1920_1020 bits access default description 31:16 ro 0x0 rx frame length 15:3 0x0 reserved 2 ro 0x0 control frame 1 ro 0x0 crc error 0 ro 0x0 length error 2.6.2.10. rx_buflvl (offset = 0x24) this read only register provides buffer levels for both rx_baddr and rx_bstat. table 2.32 receive buffer level mac0 address : 1920_0024 mac1 address : 1920_1024 bits access default description 31:16 0 reserved 23:22 0 reserved 21:16 ro 0x0 the number of buffer address taken for rx processing 15:13 0 reserved 13:8 ro 0x0 the number of buffer address not taken for rx processing 7:6 0 reserved
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 83 5:0 ro 0x0 the number of rx_bstat available for read 2.6.2.11. rx_addr_return (offset = 0x28) this read only register provides rx address used. table 2.33 rx address return mac0 address : 1920_0028 mac1 address : 1920_1028 bits access default description 31:0 ro 0x00 rx address return 2.6.2.12. ctrl_mode (offset = 0x2c) this register defines two operation modes: rx preamble and control frames. for transmit pause frame format, refer to p_frm_addr_0, p_frm_addr_1, p_frm_id, and p_frm_value starting at address offset 0x90. table 2.34 control mode register bit definition mac0 address : 1920_002c mac1 address : 1920_102c bits access default description 31:24 rw 0 reserved 23:20 rw 0 reserved 19:16 rw 0 minimum number of valid preambles for a valid rx frame 0 = no preamble byte: when sfd found, it is considered as a valid frame 1 = one preamble byte is required to be considered as a valid frame. ? 7 = seven preamble bytes are required to be considered as a valid frame. set to 0 for rmii mode.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 84 preamble of rx packet should be byte alligned. all packets with any number of byte alligned preambles can be received as valid packets. 15:8 rw 0 reserved 7:5 rw 0 pause frame slot request ( [7] & ([6] | [5]) ) need more information to describe this field. 4 rw 0 reserved 3 rw 0 tx_pause enable 0 = disable tx pause frame 1 = enable tx pause frame. 2:0 rw 0 reserved 2.6.2.13. mii_mode (offset = 0x30) mii_mode register defines various operation modes of media independent interface. table 2.35 mii mode register bit definition mac0 address : 1920_0030 mac1 address : 1920_1030 bits access default description 31:28 0 reserved 27:24 rw 0 additional output delay on tx_en, tx_er, and tx_d[3:0]. 0x0 = 0ns 0x1 = 1ns ?. 0xe = 14ns 0xf = 15ns 23:20 rw 0xf inter-transaction gap this specifies time gap (in mdc cycles) between two consecutive mii transactions when scan mode. ignored when any mode other than scan. 0x0 = reserved
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 85 0x1 = (number of gap cycle = 1) 0x2 = (number of gap cycles = 2) ? 0xe = (number of gap cycles = 14), 0xf= (number of gap cycles = 15) 19:18 0 reserved 17 rw 1 preamble 0 = no mii preamble will be used. 1 = 32-bit preamble will lead mii transaction. 16 rw 1 mdc mode 0 = gated mdc 1 = continuous mdc 15:8 rw 0x64 clock divider this field defines a host cock divider factor. the host clock can be divided by an even number, greater than 1. the default value is 0x64 (100 in decimal). 7:1 0 reserved 0 rwc 0 mii reset 0 = normal operation 1 = reset active (auto-clear after reset is done) 2.6.2.14. mii_cmd (offset = 0x34) this register defines command operation of mii table 2.36 mii command register definition mac0 address : 1920_0034 mac1 address : 1920_1034 bits access default description 31:24 0 reserved 23:19 0 reserved
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 86 18 rwc 0 read 0 = no operation or read complete 1 = read operation is in progress setting ?1? will initiate read operat ion. it will be auto cleared if read operation is completed. data read from phy will be stored at mii_rxdata (offset = 0x3c) 17 rwc 0 write 0 = no operation or write complete 1 = write operation is in progress setting ?1? will initiate write operation. it will be auto cleared if write operation is completed. transmit data should be written in mii_txdata (offset = 0x38) before setting this bit. 16 rw 0 scan / setting ?1? will initiate a scan operation 0 = no operation or scan complete 1 = scan operation is in progress scan operation will perform read operation throughout the entire range of phy id and register offsets. interrupt will be generated (if enabled) whenever single read is completed. the first phy id and register offsets to start scan operation should be written in bits[12:8] and bits[4:0] before setting this bit. the cpu needs to clear this bit to stop scan operation. 15:13 0 reserved 12:8 rw 0 phy address 7:5 0 reserved 4:0 rw 0 register address in a phy 2.6.2.15. mii_txdata (offset = 0x38) the cpu should write 16-bit tx data prior to send write command via mii_cmd register.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 87 table 2.37 mii transmit data register mac0 address : 1920_0038 mac1 address : 1920_1038 bits access default description 31:16 0 reserved 15:0 rw 0 data to be written to the phy 2.6.2.16. mii_rxdata (offset = 0x3c) the cpu can read contents of registers from phy by issuing read command via mii_cmd register. table 2.38 mii receive data register mac0 address : 1920_003c mac1 address : 1920_103c bits access default description 31:16 0 reserved 15:0 rw 0 data received from phy 2.6.2.17. length (offset = 0x44) this register defines upper and lower bound of payload length of a mac frame. it also defines maximum burst transfer length between ethernet mac and system memory. table 2.39 length register mac0 address : 1920_0044 mac1 address : 1920_1044 bits access default description 31:16 rw 0x05dc maximum payload length, default = 1500 in decimal
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 88 frames with payload of more than this value will be truncated. 15:8 rw 0x2e minimum payload length, default = 46 in decimal 7:0 rw 0x10 maximum burst transfer length in word on the system bus. default = 16 in decimal 2.6.2.18. mcast_addr_0 (offset = 0x48) this register combined with mcast_addr_1 (off set = 0x4c) provides 64-bit field to qualify multicast frame destined to this ethernet mac. only one bit out of 64-bits should be set to determine valid multicast address. the bit position to be set is calculated by applying crc over destination address field of incoming multicast frame. table 2.40 multicast address (most significant) mac0 address : 1920_0048 mac1 address : 1920_1048 bits access default description 31:0 rw 0 only one bit position should be set to determine that the current multicast frame is destined to this mac 2.6.2.19. mcast_addr_1 (offset = 0x4c) table 2.41 multicast address (least significant) mac0 address : 1920_004c mac1 address : 1920_104c bits access default description 31:0 rw 0 see multicast address 0 (offset = 0x48)
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 89 2.6.2.20. mac_addr_x0 (x = 0..7) (offset = 0x50, 0x58, ?, 0x88) this register along with the mac_addr_x1 register forms a 6-byte address field of an ethernet frame. it also provides byte ordering and valid bits for configuration. total of eight mac addresses are available. table 2.42 mac address 0 (control & byte 5, 4) mac0 address : 1920_0050, 1920_0058, 1920_0060, 1920_0068, 1920_0070, 1920_0078, 1920_0080, 1920_0088 mac1 address : 1920_1050, 1920_1058, 1920_1060, 1920_1068, 1920_1070, 1920_1078, 1920_1080, 1920_1088 bits access default description 31:24 0 reserved 23:21 0 reserved 20 rw 0 byte ordering 0 = byte 5 is the most significant byte of the address 1 = byte 0 is the most significant byte of the address 19:17 0 reserved 16 rw 0 valid 0 = the address will not be compared with incoming destination address 1 = the address will be compared with incoming destination address 15:8 rw 0 byte 5 of the ethernet mac address 7:0 rw 0 byte 4 of the ethernet mac address 2.6.2.21. mac_addr_x1 (x = 0..7) (offset = 0x54, 0x5c, ?, 0x8c) table 2.43 mac address 1 (byte 3, 2, 1, 0) mac0 address : 1920_0054, 1920_005c, 1920_0064, 1920_006c, 1920_0074, 1920_007c, 1920_0084, 1920_008c mac1 address : 1920_1054, 1920_105c, 1920_1064, 1920_106c, 1920_1074, 1920_107c, 1920_1084,
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 90 1920_108c bits access default description 31:24 rw 0 byte 3 of the ethernet mac address 23:16 rw 0 byte 2 of the ethernet mac address 15:8 rw 0 byte 1 of the ethernet mac address 7:0 rw 0 byte 0 of the ethernet mac address 2.6.2.22. p_frm_addr_0 (offset = 0x90) this register along with the p_frm_addr 1 register (offset 0x94) forms a 6-byte address field of an ethernet pause frame. it also provides byte ordering and valid bits for configuration. table 2.44 pause frame address 0 mac0 address : 1920_0090 mac1 address : 1920_1090 bits access default description 31:24 rw 0 reserved 23:21 rw 0 reserved 20 rw 0 byte ordering 0 = byte 5 is the most significant byte of the address 1 = byte 0 is the most significant byte of the address 19:17 rw 0 reserved 16 rw 0 valid 0 = the address will not be compared with incoming destination address 1 = the address will be compared with incoming destination address 15:8 rw 0x01 byte 5 of the pause frame multicast address 7:0 rw 0x80 byte 4 of the pause frame multicast address
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 91 2.6.2.23. p_frm_addr_1 (offset = 0x94) table 2.45 pause frame address 1 mac0 address : 1920_0094 mac1 address : 1920_1094 bits access default description 31:24 rw 0xc2 byte 3 of the pause frame multicast address 23:16 rw 0x00 byte 2 of the pause frame multicast address 15:8 rw 0x01 byte 1 of the pause frame multicast address 7:0 rw 0x80 byte 0 of the pause frame multicast address 2.6.2.24. p_frm_id (offset = 0x98) this register holds frame type identifier and operation code of pause frame. table 2.46 pause frame type id and op code mac0 address : 1920_0098 mac1 address : 1920_1098 bits access default description 31:16 rw 0x8808 type identifier for pause frame 15:0 rw 0x0001 operation code for pause frame 2.6.2.25. p_frm_value (offset = 0x9c) this register holds delay information of pause fr ame. this field specifies the number of delay cycles to pause tx based on mac_clk, i.e., 25mhz for 100mbps and 2.5 mhz for 10mbps.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 92 table 2.47 pause frame delay value mac0 address : 1920_009c mac1 address : 1920_109c bits access default description 31:16 0 reserved 15:0 rw 0x0018 delay value 2.6.2.26. h_tx_baddr (offset = 0xa0) this register holds base address of a frame to be transmitted via high priority tx queue (single entry). table 2.48 tx high priority queue base address mac0 address : 1920_00a0 mac1 address : 1920_10a0 bits access default description 31:0 rw 0 base address of tx frame for high priority queue 2.6.2.27. h_tx_length (offset = 0xa4) this register holds length of a frame to be transmitted via high priority tx queue (single entry). table 2.49 tx high priority queue length mac0 address : 1920_00a4 mac1 address : 1920_10a4 bits access default description 31:0 r/w 0 length of tx frame for high priority queue
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 93 2.6.2.28. tx_buf_lvl_l (offset = 0xa8) this register displays buffer levels of tx address buffer, tx length buffer, and tx address-back buffer of low priority tx queue. table 2.50 tx low priority queue level mac0 address : 1920_00a8 mac1 address : 1920_10a8 bits access default description 31:21 0 reserved 20:16 ro 0 tx address-back buffer level 15:12 0 reserved 12:8 ro 0 tx address buffer level 7:5 0 reserved 4:0 ro 0 tx length buffer level 2.6.2.29. tx_addr_bk_l (offset = 0xac) this register holds up to 15 tx addresses of low priority used in transmission. table 2.51 tx low priority queue address return mac0 address : 1920_00ac mac1 address : 1920_10ac bits access default description 31:0 ro 0 tx address back 2.6.2.30. tx_buf_lvl_h (offset = 0xb0) this register displays buffer levels of tx address buffer, tx length buffer, and tx address-back
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 94 buffer of high priority tx queue. table 2.52 tx high priority queue level mac0 address : 1920_00b0 mac1 address : 1920_10b0 bits access default description 31:21 0 reserved 20:16 ro 0 tx address-back buffer level 15:12 0 reserved 12:8 ro 0 tx address buffer level 7:5 0 reserved 4:0 ro 0 tx length buffer level 2.6.2.31. tx_addr_bk_h (offset = 0xb4) this register holds up to 15 tx addresses of high priority used in transmission. table 2.53 tx high priority queue address return mac0 address : 1920_00b4 mac1 address : 1920_10b4 bits access default description 31:0 ro 0 tx address back
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 95 2.7. uart the HMS30C7110? integrates a serial interface which supports universal asynchronous receiver / transmitter (uart) function. it is compatible with the ns16550a. the universal asynchronous receiver / transmitter supports independent 1 channel tx/rx functionality. the uart supports full duplex and it has 16 bytes internal fifos to overcome interrupt latency for receiving and sending data. the serial information exchanged between host pc and serial device has a synchronization bit (start of frame), stop bit (end of frame) and error det ection bit (parity bit). the supported parity is even, odd, forced one, and forced zero. the uart is designed to clear the cumulative clock jitter between host pc and uart device. when the uart detects the start bit, the clock gener ator synchronize internal counter to the falling edge of start bit. for this reason, the maximum tolerable jitter rate is 5 % of baud rate. the uart contains following features. z full duplex z receive fifo of 16 bytes z 6, 7 or 8 bits per character z 1 or 2 stop bits z odd parity, even parity, forced parity or none z break detection and generation z parity, overrun and framing error detection z receiver timeout interrupt z programmable baud rate generator z two modem control signals z auto-flow control
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 96 2.7.1. block diagram receiver shift register receiver fifo line control register divisor latch register line status register transmitter shift register transmit fifo modem control register modem status register interrupt enable register interrupt id register interrupt control logic receiver timing & control transmitter timing & control baud generator modem control logic apb rxd txd rts# cts# irq dtr# dsr# figure 2.10 block diagram of uart device
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 97 2.7.2. user accessible registers (base = 0x1800_0000) this section describes all base, control and stat us register inside the uart. the address field indicates a relative address in hexadecimal. the base address of uart0 is 0x18000000 and uart1 is 0x18080000. only uart1 has a hardware flow control. width specifies the number of bits in the register and access specifies the valid access types that register. where rw stands for read and write access, ro for read only access. a ?c? appended to rw or ro, indicates that some or all of the bits can be cleared after a write ?1? in corresponding bit. base address for uart 1 is 0x1808_0000. table 2.54 registers for uart name address width access description rhr 0x00 8 ro receiver holding register thr 0x00 8 wo transmitter holding register ier 0x04 4 rw interrupt enable register iir 0x08 4 ro interrupt identification register fcr 0x08 2 wo fifo control register lcr 0x0c 7 rw line control register mcr 0x10 4 rw modem control register lsr 0x14 8 ro line status register msr 0x18 8 ro modem status register dll 0x00 8 wo divisor latch lsb register dlm 0x04 8 wo divisor latch msb register *dll and dlm are accessible only when lcr bit-7 is set to ?1? 2.7.2.1. receiver holding register (rhr) this register holds the received incoming data byte. bit 0 is the least significant bit, which is transmitted and received first. received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the receive buffer register. the shift register is not accessible.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 98 table 2.55 rhr bit definition address : 1800_0000 bits access default description 31:8 0x00 reserved. 7: 0 ro 0x00 receive data this 8 bit field is loaded with receive data. the receive data is stored in fifo. rhr has the byte data first loaded in the fifo. 2.7.2.2. transmitter buffer register (thr) this register contains the data byte to be transmitted. the transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. this shift register is loaded from the transmit buffer when the transmission of the previous byte is complete. table 2.56 thr bit definition address : 1800_0000 bits access default description 31:8 0x00 reserved. 7: 0 wo 0x00 transmit data this 8 bit field is loaded with transmit data. the transmit data is double buffered. thr is copied to transmit shift register to convert serial data. 2.7.2.3. interrupt enable register (ier) this register enables five types of interrupts for the associated serial channel. each interrupt can activate the interrupt request signal. it is possible to totally disable the interrupt system by resetting bits 0 through 3 of the interrupt enable register (ier ). similarly, setting bits of the ier register to logic 1, enables the selected interrupt. disabling an interrupt prevents it from being indicated as active in the iir and from activating irq signal.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 99 table 2.57 ier bit definition address : 1800_0004 bits access default description 31:4 0x00 reserved 3 rw 0x0 modem status interrupt enable when set to logic 1 this bit enables the modem status interrupt 2 rw 0x0 receiver line status interrupt enable when set to logic 1 this bit enables the receiver line status interrupt. 1 rw 0x0 transmitter holing register empty interrupt enable when set to logic 1 this bit enables the transmitter holding register empty interrupt. 0 rw 0x0 receive data available interrupt enable when set to logic 1 this bit enables the receive data available interrupt and timeout interrupt in the fifo mode. 2.7.2.4. interrupt identification register (iir) in order to provide minimum software overhead during data character transfers, each serial channel of the uart prioritizes interrupts into four levels and records these in the interrupt identification register. the four levels of interrupt conditions in order of priority are receiver line status; received data ready; transmitter holding register empty; and modem status. table 2.58 iir bit definition address : 1800_0008 bits access default description 31:4 0x00 reserved 3 ro 0x0 this bit is set along with bit 2 when a timeout interrupt is pending. 2:1 ro 0x00 these two bits of the iir identify the highest priority interrupt pending from those shown in table 2.64.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 100 0 ro 0x0 this bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending. when bit 0 is logic 0, an interrupt is pending and the iir contents may be used as a pointer to the appropriate interrupt service routine. when bit 0 is logic 1, no interrupt is pending. table 2.59 interrupt control functions fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error or parity error or framing error or break interrupt reading the line status register 0 1 0 0 second received data available receiver data available or trigger level reached reading the receiver buffer register or the fifo drops below the trigger level 1 1 0 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char. times and there is at least 1 char. in it during this time reading the receiver buffer register 0 0 1 0 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing into the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 101 2.7.2.5. fifo control register (fcr) this is a write only register at the same location as the iir (the iir is a read only register). this register is used to enable the fifos, clear the fifos, set the rcvr fifo trigger level, and select the type of dma signaling. table 2.60 fcr bit definition address : 1800_0008 bits access default description 31:8 0x00 reserved 7:6 wo 0x00 these two bits are used to designate the interrupt trigger level. when the number of bytes in the rcvr fifo is equivalent to the designated interrupt trigger level, a received data available interrupt is activated. this interrupt must be enabled by setting ier0 0 = rcvr fifo trigger level is 1 1 = rcvr fifo trigger level is 4 2 = rcvr fifo trigger level is 8 3 = rcvr fifo trigger level is 14 5:3 0x00 reserved 2 wo 0x0 writing a 1 to fcr2 clears all bytes in the xmit fifo and resets its counter logic to 0. the shift regist er is not cleared. the 1 that is written to this bit position is self-clearing 1 wo 0x0 writing a 1 to fcr1 clears all bytes in the rcvr fifo and resets its counter logic to 0. the shift regist er is not cleared. the 1 that is written to this bit position is self-clearing. 0 0x0 reserved 2.7.2.6. line control register (lcr) the system programmer specifies the format of the asynchronous data communications exchange and sets the divisor latch access bit via the line control register (lcr). this is a read and write register. details on each bit follow:
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 102 table 2.61 lcr bit definition address : 1800_000c bits access default description 31:8 0x00 reserved 7 rw 0x0 divisor latch enable 0 = disable 1 = enable 6 rw 0x0 break control it causes a break condition to be transmitted to the receiving uart. when it is set to logic 1, the serial output is forced to the spacing state (logic 0). the break is disabled by setting this bit to logic 0. 5 rw 0x0 parity enable when this bit is logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data bit and stop bit of the serial data. 4:3 rw 0x00 parity select 0 = odd parity 1 = even parity 2 = forced one (mark parity) 3 = forced zero (space parity) 2 rw 0x0 stop bit length this bit specifies the number of stop bits transmitted or received serial character. 0 = 1 stop bit 1 = 2 stop bit 1: 0 rw 0x00 word length these two bits specify the number of data bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: 0 = 5 bits / character 1 = 6 bits / character 2 = 7 bits / character 3 = 8 bits / character
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 103 2.7.2.7. modem control register (mcr) this register controls the interface with the modem or data set. details on each bit follow: table 2.62 mcr bit definition address : 1800_0010 bits access default description 31:6 0x00 reserved 5 rw 0x0 autoflow when this bit is set, the auto-flow control is enabled. the auto-flow control can be configured by setting bit 1 and 5 of mcr as shown in table 2.68. 4 rw 0x0 loopback enable this bit provides a local loop-back feature for diagnostic testing of the associated serial channel. 3:2 0x00 reserved 1 rw 0x0 rts control this bit controls the request to send (rts#) output. bit 1 affects the rts# output in a manner identical to that described below for bit 0. 0 rw 0x0 dtr control this bit controls the data terminal ready (dtr#) output. when bit 0 is set to logic 1, the dtr# output is forced to a logic 0. when bit 0 is reset to logic 0, the dtr# output is forced to logic 1. table 2.63 autoflow control configuration bit5 bit1 description 1 1 auto-rts and auto-cts enabled 1 0 auto-cts only enabled 0 x auto-rts and auto-cts disabled
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 104 2.7.2.8. line status register (lsr) the register provides status information to the cpu concerning the data transfer. details on each bit follow: table 2.64 lsr bit definition address : 1800_0014 bits access default description 31:8 0x00 reserved 7 ro 0x0 fifo error this bit is set when there is at least one parity error, framing error or break indication if the fifo. it is cleared when the cpu reads the lsr, if there are no subsequent errors in the fifo. 6 ro 0x0 transmitter empty (temt) this bit is the transmitter empty indicator. bit 6 is set to logic 1 whenever the transmitter fifo and shift register are both empty. 5 ro 0x0 transmitter holding register empty (thre) this bit is the transmitter holding register empty indicator. this bit is set when the xmit fifo is empty; it is cleared when at least 1 byte is written to the xmit fifo. 4 ro 0x0 break interrupt (bi) this bit is the break interrupt indicator. bit 4 is set to logic 1 whenever the received data input is held in the spacing (logic 0) state for longer than a full word transmission time. the bi indicator is reset whenever the cpu reads the contents of the line status register or when the next valid character is loaded into the receiver fifo. this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. 3 ro 0x0 framing error (fe) this bit is the framing error indicator. bit 3 indicates that the
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 105 received character did not have a valid stop bit. the fe bit is set to logic 1 when the serial channel detects logic 0 during the first stop bit time. the fe indicator is reset whenever the cpu reads the contents of the line status register. this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. 2 ro 0x0 parity error (pe) this bit is the parity error (pe) indicator. bit 2 indicates that the received data character does not have the correct even or odd parity. this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. 1 ro 0x0 overrun error (oe) this bit is the overrun error indicator. bit 1 indicates that the next character received was transferred into the receiver buffer register before the cpu could read the previously received character. it is reset whenever the cpu reads the contents of the line status register. 0 ro 0x0 data ready (dr) this bit is the receive data ready indicator. bit 0 is set to logic 1 whenever a complete incoming character has been received and transferred into the receiver fifo. bit 0 is reset to logic 0 by reading all of the data in the receive fifo. 2.7.2.9. modem status register (msr) this register provides the current stat of the control lines from the modem. details on each bit follow: table 2.65 msr bit definition address : 1800_0018 bits access default description
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 106 31:6 0x00 reserved 5 ro 0x0 dsr# this bit is the complement of the data set ready input. in the loopback mode, this bit is equivalent to dtr in mcr. 4 ro 0x0 cts# this bit is the complement of the clear to send input. in the loopback mode, this bit is equivalent to rts in mcr. 3:2 0x00 reserved 1 ro 0x0 ddsr this bit is the delta data set ready indicator. it indicates that the dsr# input to the chip has changed state since the last time it was read by the cpu. 0 ro 0x0 dcts this bit is the delta clear to send indicator. it indicates that the cts# input to the chip has changed stat since the last time it was read by the cpu. 2.7.2.10. divisor latch lsb register (dll) the uart contains a programmable baud generator. the output frequency of the baud generator is 16 the divisor number. the output of baud generator drives the transmitter and receiver sections of the associated serial channel. this register contains the lower byte of the divisor number. dll is accessible only when lcr bit-7 is set to 1. table 2.66 dll bit definition address : 1800_0000 bits access default description 31:8 0x00 reserved. 7: 0 wo 0x00 lower byte of divisor number 2.7.2.11. divisor latch msb register (dlm) this register contains the higher byte of the divisor number. dlm is accessible only when lcr bit-
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 107 7 is set to 1. table 2.67 dlm bit definition address : 1800_0004 bits access default description 31:8 0x00 reserved. 7: 0 wo 0x00 higher byte of divisor number * baud rate = clock frequency (16 (divisor# + 1))
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 108 2.8. timer the HMS30C7110? integrates 3 channels of timers and each channel has 32-bit down counter. the input clock of each channel is selectable among one of the 4 clock speeds, system bus clock/1, system bus clock/4, system bus clock/16, or system bus clock/256. when the clock of the system bus is 100mhz, the timer input options are 100/25/6.25/0.4mhz. when the clock of the system is 80mhz, the timer input options are 80/20/5/0.3125mhz. the timers are fully configurable through a set of control registers. comple te descriptions of these registers are given in the register section. 2.8.1. user accessible registers (base = 0x1810_0000) this section describes all base, control and status registers inside the timer. the address field indicates a relative address in hexadecimal. width specifies the number of bits in the register and access specifies the valid access types that register. where ?rw? stands for read and write access, ?ro? for read only access. a ?c? appended to ?rw? or ?ro?, indicates that some or all of the bits can be cleared after a write ?1? in corresponding bit. table 2.68 registers for timer name address width access description clock selection 0x00 3x2 rw input clock selection for 3 channels timer control 0x04 3x2 rw channel enable/disable timer interval 0 0x08 32 rw reload value for timer channel 0 timer interval 1 0x0c 32 rw reload value for timer channel 1 timer interval 2 0x10 32 rw reload value for timer channel 2 timer value 0 0x14 32 rw channel 0 current timer value timer value 1 0x18 32 rw channel 1 current timer value timer value 2 0x1c 32 rw channel 2 current timer value int src 0x20 3 rw interrupt pending register int enable 0x24 3 rw interrupt enable register
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 109 2.8.1.1. clock selection this register contains clock division values (pre-scalar) for 3 channels. table 2.69 clock selection register bit definition address : 1810_0000 bits access default description 31:10 reserved 9: 8 rw 0 clock select for timer 2 0 = system bus clock 1 = system bus clock 4 2 = system bus clock 8 3 = system bus clock 256 7: 6 reserved 5: 4 rw 0 clock select for timer 1 0 = system bus clock 1 = system bus clock 4 2 = system bus clock 8 3 = system bus clock 256 3: 2 reserved 1: 0 rw 0 clock select for timer 0 0 = system bus clock 1 = system bus clock 4 2 = system bus clock 8 3 = system bus clock 256 2.8.1.2. timer control this register includes timer enable and clear bits for 3 channels.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 110 table 2.70 timer control register bit definition address : 1810_0004 bits access default description 31:10 reserved 9 w 0 timer 2 clear writing ?1? to this bit clears the channel 2 counter. 8 rw 0 timer 2 enable 0 = timer2 disable 1 = timer2 enable 7: 6 reserved 5 w 0 timer 1 clear writing ?1? to this bit clears the channel 1 counter. 4 rw 0 timer 1 enable 0 = timer1 disable 1 = timer1 enable 3: 2 reserved 1 w 0 timer 0 clear writing ?1? to this bit clears the channel 0 counter. 0 rw 0 timer 0 enable 0 = timer0 disable 1 = timer0 enable 2.8.1.3. timer interval 0~2 these registers include timer values. table 2.71 timer interval register bit definition address : 1810_0008, 1810_000c, 1810_0010 bits access default description 31: 0 rw 0 interval this 32-bit field contains the interval value that is loaded to the down
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 111 counter to recount. 2.8.1.4. timer value 0~2 these registers show the current values of the down counter. table 2.72 current timer value register bit definition address : 1810_0014, 1810_0018, 1810_001c bits access default description 31: 0 ro 0 ctv (current timer value) this 32-bit field indicates the present value of internal down counter. 2.8.1.5. int src this register has 3 timer interrupts that occur every time the counter reaches zero. table 2.73 interrupt source register bit definition address : 1810_0020 bits access default description 31: 3 0 reserved 2 rw 0 expire timer 2 this bit indicates that the channel 2 down counter reaches zero value. 1 rw 0 expire timer 1 this bit indicates that the channel 1 down counter reaches zero value. 0 rw 0 expire timer 0 this bit indicates that the channel 0 down counter reaches zero value. 2.8.1.6. int enable this register includes interrupt enable bits.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 112 table 2.74 interrupt enable address : 1810_0024 bits access default description 31: 3 reserved 2 rw 0 expire timer 2 enable 1 rw 0 expire timer 1 enable 0 rw 0 expire timer 0 enable
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 113 2.9. gpio the HMS30C7110? integrates a gpio module that supports 21 gpio (general purpose input / output) ports. 3 gpio out of 21 are dedicated to gpio feature and others are muxed to other features. each port is configurable with input or output mode. the initial modes of all gpio pins are set to input, so when to use in output mode, it is highly recommended to pull-up or pull-down the ports to prevent annoying vibration caused by temporary high impedance state during reset and initialization. the gpio is capable of interrupting the mcu when input signal triggers, and it supports one of the four kinds of interrupt source signal. level trigger high/low and edge trigger rising/falling signal. the gpio is fully configurable through a set of control registers. complete descriptions of these registers are given in the register section. 2.9.1. user accessible registers (base = 0x1820_0000) this section describes all base, control and status registers inside the gpio module. the address field indicates a relative address in hexadecimal. width specifies the number of bits in the register and access specifies the valid access types to that register. ?rw? stands for read and write access and ?ro? for read only access. a ?c? appended to ?rw? or ?ro? indicates some or all of the bits can be cleared after writing ?1? to the corresponding bit. table 2.75 registers for gpio name address width access description gpo data 0x00 9 rw gpo data to i/o pins gpi data 0x04 12 ro gpi data from i/o pins gpio direction 0x08 9 rw direction for i/o pins int src 0x0c 16 rw interrupt source int enable 0x10 16 rw interrupt enable int mode 0x14 16 rw detection mode of interrupt
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 114 int level 0x18 16 rw detection level of interrupt 2.9.1.1. gpo data the gpo data register has gpo output data that is put on the external pins. this value can be read also. each gpo has nothing to do with same numbered gpi, which means independent operation. table 2.76 gpo data register bit definition address : 1820_0000 bits access default description 31: 9 reserved 8: 0 rw 0 gpo data this 9-bit field is output to the gpo pins and the gpios when set to output mode. 2.9.1.2. gpi data the gpi data register shows the gpi input data on the gpio pins. table 2.77 gpi data register bit definition address : 1820_0004 bits access default description 31:12 reserved 11: 0 ro 0 gpi data this 12-bit field shows the status of gpi pins and the stautus of gpio pins regardless the direction of gpios or the mode of gpi, dedicated mode or gpi mode. 2.9.1.3. gpio direction the gpio direction register controls the direction of gpio pins and chooses the function of gpis and gpos.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 115 table 2.78 gpio direction register bit definition address : 1820_0008 bits access default description 31:9 0x00 reserved 8:3 rw 0x00 gpo function these pins set the coressponding pins to either dedicated function or gpo. 0 = use for specific features 1 = use for gpi or gpo 2:0 rw 0x00 gpio direction this 3-bits field controls the direction of gpio pads. 0 = input mode 1 = output mode 2.9.1.4. int src the interrupt source register indicates which input pin is triggered. table 2.79 interrupt source register bit definition address : 1820_000c bits access default description 31: 16 0x00 reserved 15: 0 roc 0x00 int source this 16-bits field indicates which gpi pin(s) generated interrupt(s). bit 0 through 7 generate external interrupt 0 through 7 respectively. bit 8 through 15 generate gpio interrupt. 2.9.1.5. int enable the interrupt enable register chooses the interrupt sources being used.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 116 table 2.80 the bit definition of the interrupt enable register address : 1820_0010 bits access default description 31: 16 0x00 reserved 15: 0 rw 0x00 int enable this 16-bits field enables the gpi interrupts. 0 = disable 1 = enable 2.9.1.6. int mode the interrupt mode register chooses the interrupt mode of either level trigger or edge trigger. table 2.81 interrupt mode register bit definition address : 1820_0014 bits access default description 31: 16 0x00 reserved 15: 0 rw 0x00 int mode this 16-bits field controls the interrupt mode of each gpi pins. 0 = level trigger 1 = edge trigger 2.9.1.7. int level the interrupt level register selects active level of interrupt sources when in level triggering mode, active low or active high. table 2.82 interrupt level register bit definition address : 1820_0018 bits access default description
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 117 31:16 0x00 reserved 15: 0 rw 0x00 int level this 16-bits field controls the active level of interrupt request on each gpi pins. 0 = low active for level / falling edge for edge trigger 1 = high active for level / rising edge for edge trigger 2.10. spi the HMS30C7110? integrates an serial peripheral interface (spi) module which is used for interfacing the serial rom or serial interface devices such as pcm audio codec. the spi of HMS30C7110? generates serial clock (cclk), serial data out (cdout), serial data in (cdin) and chip select (nccs). the clock speed is selectable by programming the internal register. the spi also supports the 8bit, 16bit and 32bit io devices. the complete descriptions of these registers are given in the register section. 2.10.1. block diagram the spi of HMS30C7110? consists of several blocks such as register file and serial interface core module.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 118 shift register fifo (32 bytes) fsm register file (apb slave) rx data shift register tx data baud generator cdout cdin fifo (32 bytes) cclk nccs register bus figure 2.11 block diagram of spi
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 119 2.10.2. user accessible registers (base = 0x1840_0000) this section describes all base, control and status register inside spi. the address field indicates a relative address in hexadecimal. the base address is 0x18500000. width specifies the number of bits in the register and access specifies the valid access types that register. where rw stands for read and write access, ro for read only access. a ?c? appended to rw or ro, indicates that some or all of the bits can be cleared after a write ?1? in corresponding bit. table 2.83 registers for spi name address width access description spi control 0x00 9 rw spi baud rate and enable control spi mode0 0x04 8 rw recovery timing control & tx start reserved 0x08 reserved reserved 0x0c reserved reserved 0x10 reserved reserved 0x14 reserved tx data 0x18 8 rw transmit data rx data 0x1c 8 rw receive data int src 0x20 1 roc interrupt source int enable 0x24 1 rw interrupt enable status 0x28 1 r rx empty
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 120 2.10.2.1. spi control (offset = 0x00) this register includes spi enable bit and baud rate setting value. table 2.84 spi control register bit definition address : 1840_0000 bits access default description 31:9 0 reserved 8 rw 0 enable 0 = spi clock disable 1 = spi clock enable 7:0 rw 0 baud rate one clock period = (baudrate+1) clkin 2.10.2.2. spi mode 0 (offset = 0x04) these registers include recovery cycle field and data width field. table 2.85 configuration register bit definition address : 1840_0004 bits access default description 31:12 0 reserved 7:4 rw 0 recovery time this 4-bit field is used for making recovery time from one access cycle to the next access cycle. 3:1 0 reserved 0 rw 0 tx start this one bit field is used to start transfer of tx fifo data. 2.10.2.3. tx data (offset = 0x18) this register is writing path to 32 bytes tx fifo.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 121 table 2.86 tx data register bit definition address : 1840_0018 bits access default description 31:8 0 reserved 7:0 rw 0 tx data 2.10.2.4. rx data (offset = 0x20) this register is reading path of 32 bytes rx fifo. table 2.87 rx data register bit definition address : 1840_001c bits access default description 31:8 0 reserved 7: 0 rw 0 rx data 2.10.2.5. int src this register includes spi interrupt source bits. table 2.88 interrupt source register bit definition address : 1840_0020 bits access default description 31: 1 0 reserved 0 rw 0 tx done 2.10.2.6. int enable this register includes spi interrupt enable bits.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 122 table 2.89 interrupt mask register bit definition address : 1840_0024 bits access default description 31:1 0 reserved 0 rw 0 tx done enable 2.10.2.7. status this register includes spi rx status bits. table 2.90 spi status register bit definition address : 1840_0028 bits access default description 31: 1 0 reserved 0 r 0 tx empty
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 123 2.11. dma HMS30C7110? supports two-channel dma controller that is located between the system bus and the peripheral bus. each channel of dma controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. in other words, each channel can handle the following four cases: 1) both source and destination are in the system bus, 2) source is in the system bus while destination is in the peripheral bus, 3) sources in the peripheral bus while destination is in the system bus, 4) both source and destination are in the peripheral bus. the main advantage of dma is that it can tran sfer data without any cpu intervention. the operation of dma can be initiated by s/w, the request from internal peripherals or the external request pins. 2.11.1. user accessible registers (base = 0x1910_0000) there are seven control registers for each dma channel (since there are two channels, the total number of control registers is 14). four of them are to control the dma transfer, and other three are to see the status of dma controller. the details of those registers for a channel are as follows. 2.11.1.1. dma initial source register (disrc, offset = 0x00, 0x20) table 2.91 dma initial source register dma0 address : 1910_0000 dma1 address : 1910_0020 field name bit description loc [31] bit 31 is used to select the location of source. 0: the source is in the system bus, 1: the source is in the peripheral bus inc [30] bit 30 is used to select the address increment. increment unit is determined by ds of dcon. 0 = increment 1= fixed
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 124 s_addr [29:0] these bits are the base address (start address) of source data to transfer 2.11.1.2. dma initial destination register (didst, offset = 0x04, 0x24) table 2.92 dma initial destination register dma0 address : 1910_0004 dma1 address : 1910_0024 field name bit description loc [31] bit 31 is used to select the location of destination. 0: the destination is in the system bus, 1: the destination is in the peripheral bus inc [30] bit 30 is used to select the address increment. 0 = increment 1= fixed s_addr [29:0] these bits are the base address (start address) of destination to transfer 2.11.1.3. dma control register (dco n, offset = 0x08, 0x28) table 2.93 dma control register dma0 address : 1910_0008 dma1 address : 1910_0028 field name bit description dmd_hs [30] select one between demand mode and handshake mode. 0 : demand mode is selected 1 : handshake mode is selected. sync. [29] select dreq/dack synchronization 0: dreq and dack are synchronized to pclk. 1: dreq and dack are synchronized to hclk. int [28] enable/disable the inte rrupt setting for tc(terminal count) 0: tc interrupt is disabled. 1: interrupt is generated when all the transfer is done.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 125 ts [27] select the transfer size of a transfer 0: a single transfer is performed. 1: a burst transfer of length four is performed. servmode [26] select the service mode between single service mode and whole service mode 0: single service mode 1: whole service mode hwsrcsel [25:24] select dma request source for each dma. swhw_sel [23] select the dma source between software (s/w request mode) and hardware (h/w request mode). 0: s/w request mode 1: h/w request mode reload [22] set the reload on/off option. 0: auto reload is performed. 1: channel is turned off after tc reaches. ds [21:20] data size to be transferred. 0: 8-bit (byte), 1 : 16-bit (half-word), 2: 32-bit (word) tc [19:0] initial transfer count (or transfer beat). note that the actual # of bytes that are transfered is obtained bt the following equation: dsz * tsz * tb, where dsz, tsz, and tb represent data size, transfer size, and transfer beats, respectively. 2.11.1.4. dma status register (dstat, offset = 0x0c, 0x2c) this register shows the current value of transfer counter(tc) and whether this channel is busy or idle. table 2.94 dma status register dma0 address : 1910_000c dma1 address : 1910_002c field name bit description
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 126 rsvd [30:22] reserved status [21:20] dma status. 0: ready(or idle), 1: busy, 2: error ctc [19:0] current transfer count (or transfer beat). 2.11.1.5. dma current source register (dcsrc, offset = 0x10, 0x30) this register shows the value of current source address of the transfer. so only least 30 bits are valid. dma0 address : 1910_0010 dma1 address : 1910_0030 field name bit description [29:00] current source address 2.11.1.6. current destination register (dcdst, offset = 0x14, 0x34) this register shows the value of current destination address of the transfer. dma0 address : 1910_0014 dma1 address : 1910_0034 field name bit description [29:00] current destination address 2.11.1.7. dma mask trigger register (masktrig, offset = 0x18, 0x38) table 2.95 dma mask trigger register dma0 address : 1910_0018 dma1 address : 1910_0038 field name bit description
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 127 stop [2] stop the dma operation. 1: dma stops as soon as the current atomic transfer ends. note : if there is no current atomic transfer, dma stops immediately. due to possible current atomic transfer, "stop" may take several cycles. the finish of "stop" operation can be detected by waiting until the channel on/off bit is set to off. this stop is actual "stop". it means that if dma starts again all the values including tc start from initial values. on_off [1] dma channel on/off bit. 0: dma channel is turned off. (dma request to this channel is ignored.) 1: dma channel is turned on and the dma request is handled. note : this bit is automatically set to off if we set the control register (dcon) to "no auto reload" and/or this register (masktrig) to "stop". note that when "no auto reload" is set, this bit becomes "off" when tc becomes 0. on the other hand, if "stop" is set, this bit becomes "off" as soon as the current automic transfer finishes. this bit should not be changed manually during dma operation. sw_trig [0] trigger the dma channel in s/w. 1: it requests a dma operation to this controller.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 128 2.12. intc the interrupt controller of HMS30C7110? receives the request from 21 interrupt sources. among 21, 8 come from outside of chip, i.e., external interrupt sources, and remaining 13 come from internal sources such as dma controller, enet mac, and etc. the role of the interrupt controller is to ask for irq and/or nmi to the arm7tdmi after selecting one among 21 sources based on the arbitration rule. the arbitration is performed by the hardware priority logic and the result is written to the interrupt pending register to let users to know which interrupt has been requested. interrupt mode intc supports 2 types of interrupt modes, nmi and irq. the mode of each interrupt source can be set by programming interrupt mode register. among 21 sources, only one, generally very urgent one such as power failure can be set to operate as nmi. interrupt pending register there are two interrupt pending registers. one is source pending register (srcpnd) and the other is interrupt pending register (intpnd). these pending registers indicate whether or not an interrupt request is pending. when the interrupt sources request interrupt services the corresponding bits of srcpnd register are set to 1, and at the next cl ock cycle one bit of intpnd register corresponding to the highest priority one is set to 1 after the arbitration process. if some of interrupts are masked (by programming mask register), the corresponding bits of intpnd register are not set to 1, while the corresponding bits of srcpnd register are se t to 1. when a pending bit of intpnd register is set, irq is generated and goes to cpu. the srcpnd and intpnd registers can be read and written. the interrupt service routine must clear the pending condition by writing a 1 to the corresponding bit of srcpnd register first and then clear the pending condition in intpnd registers by writing 1. the nmi shares the srcpnd register with irq, bu t it does not go through the arbitration logic and directly goes to cpu for a fast service. so, in the service routine of nmi, user needs to clear only the srcpnd register. interrupt mask register
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 129 this register is used to mask the requests of some interrupt sources. if a bit of the register is set to 1, it indicates that the corresponding interrupt is disabled. if it is set to 0, the corresponding interrupt will be serviced normally. this mask register actu ally resides after the srcpnd register and affects the effective value of srcpnd register going to arbitration logic and nmi generation logic. therefore, even for the masked requests, srcpnd register reflects their arrival as usual. interrupt sources interrupt controller supports 21 interrupt sources as shown in the below table. table 2.96 interrupt source register sources bit descriptions arbiter group int_uart1 29 uart1 interrupt arb5 int_uart0 28 uart0 interrupt arb5 int_spi 27 spi interrupt arb4 reserved 26 reserved arb4 cardbus 22 cardbus er ror interrupt arb4 card irq 21 irq from installed card arb3 pcmcia 20 pcmcia interrupt including card detection arb3 int_gpio 19 gpio interrupt (from gpi8 ~ gpi10) arb3 int_dma1 18 dma channel 1 interrupt arb3 int_dma0 17 dma channel 0 interrupt arb3 int_enet1 14 enet mac 1 interrupt arb2 int_enet0 11 enet mac 0 interrupt arb2 int_timer 10 timer interrupt arb2 int_ext7 7 external interrupt 7 (from gpi7) arb1 int_ext6 6 external interrupt 6 (from gpi6) arb1 int_ext5 5 external interrupt 5 (from gpi5) arb1 int_ext4 4 external interrupt 4 (from gpi4) arb1 int_ext3 3 external interrupt 3 (from gpi3) arb0 int_ext2 2 external interrupt 2 (from gpio2) arb0 int_ext1 1 external interrupt 1 (from gpio1) arb0
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 130 int_ext0 0 external interrupt 0 (from gpio0) arb0 arbitration block the priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first- level arbiters and one second-level arbiter as shown in the following figure. arb6 arb2 arb3 arb4 arb5 arb1 arb0 req1: int_ext0 req2: int_ext1 req3: int_ext2 req4: int_ext3 req1: int_ext5 req2: int_ext6 req3: int_ext7 req4: reserved req0: int_ext4 req5: reserved req1: int_enet0 req2: reserved req3: reserved req4: int_enet1 req0: int_timer req5: reserved req1: int_dma0 req2: int_dma1 req3: int_gpio req4: int_pcmcia req0: reserved req5: int_pcmirq req1: reserved req2: reserved req3: reserved req4: int_i2c req0: int_cardbus req5: int_spi req1: int_uart0 req2: int_uart1 req3: reserved req4: reserved req0 req1 req2 req3 req4 req5 irq figure 2.12 arbitration block diagram each arbiter can handle six interrupt requests based on the one bit arbiter mode control
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 131 (arb_mode) and two bits of selection control signals (arb_sel) as follows: ? if arb_sel bits are 00b, the priority order is req0, req1, req2, req3, req4, and req5. ? if arb_sel bits are 01b, the priority order is req0, req2, req3, req4, req1, and req5. ? if arb_sel bits are 10b, the priority order is req0, req3, req4, req1, req2, and req5. ? if arb_sel bits are 11b, the priority order is req0, req4, req1, req2, req3, and req5. note that req0 of an arbiter is always the highest priority, and req5 is the lowest one. in addition, by changing the arb_sel bits, we can rotate the priority of req1 - req4. here, if arb_mode bit is set to 0, arb_sel bits are not automatically changed, thus the arbiter operates in the fixed priority mode. (note that even in this mode, we can change the priority by manually changing the arb_sel bits.). on the other hand, if arb_mode bit is 1, arb_sel bits are changed in rotation fashion, e.g., if req1 is serviced, arb_sel bits are changed to 01b automatically so as to make req1 the lowest priority one. the detailed rule of arb_sel change is as follows. ? if req0 or req5 is serviced, arb_sel bits are not changed at all. ? if req1 is serviced, arb_sel bits are changed to 01b. ? if req2 is serviced, arb_sel bits are changed to 10b. ? if req3 is serviced, arb_sel bits are changed to 11b. ? if req4 is serviced, arb_sel bits are changed to 00b. 2.12.1. user accessible registers (base = 0x1930_0000) there are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority regi ster, and interrupt pending register. all the interrupt requests from the interrupt sources are first registered in the source pending register. they are divided into two groups based on the interrupt mode register, i.e., one nmi request and the remaining irq requests. arbitration process is performed for the multiple irq requests based on the priority register. 2.12.1.1. source pending register (srcpnd, offset = 0x00) srcpnd register is composed of 32 bits each of which is related to an interrupt source. each bit is
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 132 set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. by reading this register, we can see the interrupt sources waiting for their requests to be serviced. note that each bit of srcpnd register is automatically set by the interrupt sources regardless of the masking bits in the intm ask register. in addition, it is not affected by the priority logic of interrupt controller. in the interrupt service routine for a specific interrupt source, the corresponding bit of srcpnd register has to be cleared to get the interrupt request from the same source correctly. if you return from the isr (interrupt service routine) without clear ing the bit, interrupt controller operates as if another interrupt request comes in from the same source. in other words, if a specific bit of srcpnd register is set to 1, it is always considered as a valid interrupt request waiting to be serviced. the specific time to clear the corresponding bit depends on the user's requirement. the bottom line is that if you want to receive another valid request from the same source you should clear the corresponding bit first, and then enable the interrupt. you can clear a specific bit of srcpnd register by writing a data to this register. it clears only the bit positions of srcpnd corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are with no change. table 2.97 source pending register address : 1930_0000 register address r/w description value srcpnd 0x00 r/w 0 = the interrupt has not been requested 1 = the interrupt source has asserted the interrupt request 0x00000000 bit field bit field bit field bit field 31 reserved 23 reserved 15 reserved 7 int_ext7 30 reserved 22 int_cardbus 14 int_enet1 6 int_ext6 29 int_uart1 21 int_pcmirq 13 reserved 5 int_ext5 28 int_uart0 20 int_pcmcia 12 reserved 4 int_ext4 27 int_spi 19 int_gpio 11 int_enet0 3 int_ext3 26 reserved 18 int_dma1 10 int_timer 2 int_ext2 25 reserved 17 int_dma0 9 reserved 1 int_ext1
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 133 24 reserved 16 reserved 8 reserved 0 int_ext0 2.12.1.2. mode register (intmod, offset = 0x04) this register is composed of 32 bits each of which is related to an interrupt source. if a specific bit is set to 1, the corresponding interrupt is processed as the nmi request. otherwise, it is processed as a normal irq. note that at most only one interrupt source can be serviced in the nmi mode. (you should use the nmi mode only for the urgent interrupt.) thus, only one bit of intmod can be set to 1 at most. this register is write-only one, thus it cannot be read out. table 2.98 interrupt mode register address : 1930_0004 register address r/w description reset value intmod 0x04 w 0 = irq mode, 1 = nmi mode 0x00000000 each field and the corresponding bit position are the same as those of srcpnd register. 2.12.1.3. interrupt mask register (intmsk, offset = 0x08) each of the 32 bits in the interrupt mask register is related to an interrupt source. if you set a specific bit to 1, the interrupt request from corresponding interrupt source is not serviced by cpu. (note that even in such a case, the corresponding bit of srcpnd register is set to 1). if the mask bit is 0, the interrupt request can be serviced. table 2.99 interrupt mask register address : 1930_0008 register address r/w description reset value intmsk 0x08 r/w 0 = interrupt service is available 0xffffffff
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 134 1 = interrupt service is masked each field and the corresponding bit position are same to those of srcpnd register. 2.12.1.4. priority register (priority, offset = 0x0c) table 2.100 priority register address : 1930_000c register address r/w description reset value priority 0x0c w irq priority control register 0x07f field bit description reset value arb_sel6 20:19 arbiter 6 priority 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 00 arb_sel5 18:17 arbiter 5 priority 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 00 arb_sel4 16:15 arbiter 4 priority 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 00 arb_sel3 14:13 arbiter 3 priority 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 00 arb_sel2 12:11 arbiter 2 priority 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 00 arb_sel1 10:9 arbiter 1 priority 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 00 arb_sel0 8:7 arbiter 0 priority 00
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 135 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 arb_mode6 6 arbiter 6 rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode5 5 arbiter 5 rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode4 4 arbiter 4 rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode3 3 arbiter 3 rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode2 2 arbiter 2 rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode1 1 arbiter 1 rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode0 0 arbiter 0 rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 2.12.1.5. interrupt pending register (intpnd, offset = 0x10) each of the 32 bits in the interrupt pending r egister shows whether the corresponding interrupt request is the highest priority one that is unmaske d and waits for the interrupt to be serviced. since intpnd is located after the priority logic, only one bit can be set to 1 at most, and that is the very interrupt request generating irq to cpu. in interrupt service routine for irq, you can read this register to determine the interrupt source to be serviced among 23 sources. like the srcpnd, this register has to be cleared in the interrupt service routine. we can clear a specific bit of intpnd register by writing a data to this register. it clears only the bit positions of intpnd corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are with no change. table 2.101 interrupt pending register address : 1930_0010
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 136 register address r/w description reset value intpnd 0x10 r/w 0 = the interrupt has not been requested 1 = the interrupt source has asserted a request 0x00000000 each field and the corresponding bit position are the same as those of srcpnd register. 2.12.1.6. interrupt offset register (intofs, offset = 0x14) if intpnd[n] is set to 1 (due to interrupt reques ts from sources), number ?n? is shown in this register. this is for the ease of an interrupt target address computation, i.e., target address = intofs << 2. note that the valid value of this register is 0 ? 31 when an interrupt occurs. if it is 32, it means that there happens no interrupts, i.e., intpnd = 0. table 2.102 interrupt offset register address : 1930_0014 register address r/w description reset value intofs 0x14 r ?n? in 0 ? 31 if intpnd[n] is set to 1. 32 if there happens no interrupt. 0x00000020
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 137 2.13. pcmcia controller the HMS30C7110? integrates a pcmcia controller which supports 16-bits pc card and 32-bits pc card (cardbus) functionalities. the pcmcia controller supports 1 socket 16-bits pc card or 1 socket cardbus card. 2.13.1. user accessible registers (base = 0x1940_0000) this section describes all base, control and status register inside the pcmcia. the address field indicates a relative address in hexadecimal. the base address for 16-bits pc card is 0x19400000 and the base address for cardbus is 0x19480000. width specifies the number of bits in the register and access specifies the valid access types that register. where rw stands for read and write access, ro for read only access. a ?c? appended to rw or ro, indicates that some or all of the bits can be cleared after a write ?1? in corresponding bit. table 2.103 registers for pcmcia name address width access description idr 0x00 32 ro identification register isr 0x04 32 ro interface status register icr 0x08 32 rw interface control register gcr 0x0c 32 rw general control register cscr 0x10 32 roc card status change register ier 0x14 32 rw interrupt enable register setup0 0x18 32 rw setup timing 0 register for io command0 0x1c 32 rw command timing 0 register for io recovery0 0x20 32 rw recovery timing 0 register for io setup1 0x24 32 rw setup timing 1 register for common memory command1 0x28 32 rw command timing 1 register for common memory
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 138 recovery1 0x2c 32 rw recovery timing 1 register for common memory setup2 0x30 32 rw setup timing 2 register for attribute memory command2 0x34 32 rw command timing 2 register for attribute memory recovery2 0x38 32 rw recovery timing 2 register for attribute memory start0 0x40 32 rw i/o start address 0 end0 0x44 32 rw i/o end address 0 start1 0x48 32 rw i/o start address 1 end1 0x4c 32 rw i/o end address 1 gpo_enable0 0x50 32 rw direction control for gpio-0 gpo_enable1 0x54 32 rw direction control for gpio-1 gpo_0 0x58 32 rw output value for gpio-0 gpo_1 0x5c 32 rw output value for gpio-1 gpi_0 0x60 32 rw input value of gpi-0 gpi_1 0x64 32 rw input value of gpi-1 table 2.104 registers for cardbus name address width access description command 0x00 32 rw cardbus bridge command register status 0x04 32 ro cardbus bridge status register retry time 0x08 32 rw retry time control register clk select 0x0c 32 rw clock speed selection register 2.13.1.1. identification register (idr) table 2.105 idr bit definition address : 1940_0000 bits access default description
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 139 31:8 0x00 reserved. 7: 0 ro 0x00 id number this 8bit field ?0x82?. 2.13.1.2. interface status register (isr) table 2.106 isr bit definition address : 1940_0004 bits access default description 31:8 0x00 reserved. 7 ro 0 vs2 this bit reflects the state of the vs2 pin of the pcmcia. 6 ro 0 vs1 this bit reflects the state of the vs1 pin of the pcmcia. 5 ro 0 ready/busy signal status this bit reflects the state of the ready pin of the pcmcia. 4 ro 0 memory write protect signal status this bit reflects the state of the wp pin of the pcmcia. 3 ro 0 card detect 2 signal status this bit reflects the state of the cd2 pin of the pcmcia. 2 ro 0 card detect 1 signal status this bit reflects the state of the cd1 pin of the pcmcia. 1 0 reserved 0 ro 0 status change signal status this bit reflects the state of the stschg pin of the pcmcia. 2.13.1.3. interface control register (icr) table 2.107 icr bit definition
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 140 address : 1940_0008 bits access default description 31:4 0x00 reserved. 7 rw 0 vs2 signal output 0 = drive logic 0 value to vs2 pin 1 = input mode or pull-up to vs2 pin 6 rw 0 vs1 signal output 0 = drive logic 0 value to vs1 pin 1 = input mode or pull-up to vs1 pin 5:0 0x0 reserved 2.13.1.4. general control register (gcr) table 2.108 gcr bit definition address : 1940_000c bits access default description 31:6 0x00 reserved 6:5 rw 0x0 pcmcia is i/o 0 = socket configured for the memory-only interface 1 = socket configured for i/o and memory interface 2 = socket configured for dma interface 3 = reserved 4:2 0x0 reserved 1 rw 0x0 spi and uart1 mode when set to logic 1, this bit converts the cd2~1 pins and vs2~1 pins to the spi functional pins and ctrdy, cframe,cad19 and cserr to cts,rts,txd and rxd respectively for uart1 flow control . 0 rw 0x0 cardbus mode 0 = 16-bit pc card mode 1 = cardbus mode
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 141 2.13.1.5. card status change register (cscr) table 2.109 cscr bit definition address : 1940_0010 bits access default description 31:4 0x00 reserved 3 roc 0x card detect change detected this bit will be set when a transition (low to high or high to low) has occurred on the cd2~1 pins. this bit is reset to 0 when this register is read. 2 roc 0x0 ready change detected this bit will be set when a transition (low to high or high to low) has occurred on the ready pin. this bit is reset to 0 when this register is read. this bit has meaning only when the socket is configured for the memory-only interface. in the i/o and memory interface it reads back as 0. 1 0x0 reserved 0 roc 0x0 status change detected this bit will be set when a transition (low to high or high to low) has occurred on the stschg pin. this bit is reset to 0 when this register is read. 2.13.1.6. interrupt enable register (ier) table 2.110 ier bit definition address : 1940_0014 bits access default description
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 142 31:4 0x00 reserved 3 rw 0x interrupt enable for card detect change detected 2 rw 0x0 interrupt enable for ready change detected 1 0x0 reserved 0 rw 0x0 interrupt enable for status change detected 2.13.1.7. setup timing registers (setup0, setup1, setup2) table 2.111 setup bit definition address : 1940_0018 bits access default description 31:8 0x00 reserved 7:6 rw 0x0 setup timing prescaler select for this timing set, this field selects prescaler value to prescale the setup value to determine the number of clocks of setup time from valid address before the pcmcia command goes active. 00 = 1 01 = 16 10 = 256 11 = 4096 5:0 rw 0x00 setup timing multiplier value for this timing set, this field selects setup value from 0 to 63 to be multiplied with prescaler value to determine the number of clocks of setup time from valid address before the pc card command goes active. 2.13.1.8. command timing registers (command0, command1, command2) table 2.112 command bit definition
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 143 address : 1940_001c address : 1940_0028 address : 1940_0034 bits access default description 31:8 0x00 reserved 7:6 rw 0x0 command timing prescaler select for this timing set, this field selects prescaler value to prescale the command value to determine the number of clocks of command active time. 00 = 1 01 = 16 10 = 256 11 = 4096 5:0 rw 0x00 command timing multiplier value for this timing set, this field selects command value from 0 to 63 to be multiplied with prescaler value to determine the number of clocks of command active time. 2.13.1.9. recovery timing registers (recovery0, recovery 1, recovery 2) table 2.113 recovery bit definition address : 1940_0020 address : 1940_002c address : 1940_0038 bits access default description 31:8 0x00 reserved 7:6 rw 0x0 recovery timing prescaler select for this timing set, this field selects prescaler value to prescale the command value to determine the number of clocks of recovery time. 00 = 1 01 = 16
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 144 10 = 256 11 = 4096 5:0 rw 0x00 recovery timing multiplier value for this timing set, this field selects command value from 0 to 63 to be multiplied with prescaler value to determine the number of clocks of recovery time. 2.13.1.10. start address for i/o (start0, start1) table 2.114 start address bit definition address : 1940_0040 address : 1940_0048 bits access default description 31:30 0x00 bank width 00 = 8-bit 01 = 16-bit 10 = auto detect using iois16n 11 = reserved 29:26 0x0 reserved 25:0 rw 0x00 start address this 26-bit field is used for decoding start address for io bank. 2.13.1.11. end address for i/o (end0, end1) table 2.115 end address bit definition address : 1940_0044 address : 1940_004c bits access default description 31:26 0x0 reserved
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 145 25:0 rw 0x00 end address this 26-bit field is used for decoding end address for io bank. 2.13.1.12. gpio direction control (gpo_enable0, gpo_enable1) table 2.116 gpio direction registers bit definition address : 1940_0050 address : 1940_0054 bits access default description 31:0 0x0 gpo direction 0 = input: all pcmcia pins are used for pcmcia feature 1 = output: all pcmcia pins are used for gpio feature 2.13.1.13. output value for gpio (gpo_0, gpo_1) table 2.117 gpo registers bit definition address : 1940_0058 address : 1940_005c bits access default description 31:0 0x0 gpo values 2.13.1.14. input value of gpio (gpi_0, gpi_1) table 2.118 gpi registers bit definition address : 1940_0060 address : 1940_0064 bits access default description
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 146 31:0 0x0 gpi values table 2.119 gpio muxing table pin name gpio pin name gpio pin name gpio cad0 gpio-00 cad21 gpio-20 cad16 gpio-40 cad1 gpio-01 cad22 gpio-21 raddr18 gpio-41 cad3 gpio-02 cad23 gpio-22 ncblock gpio-42 cad5 gpio-03 cad24 gpio-23 ncstop gpio-43 cad7 gpio-04 cad25 gpio-24 ndevsel gpio-44 ncbe0 gpio-05 cad26 gpio-25 ntrdy gpio-45 cad9 gpio-06 cad27 gpio-26 nframe gpio-46 cad11 gpio-07 cad29 gpio-27 cad17 gpio-47 cad12 gpio-08 raddr2 gpio-28 cad19 gpio-48 cad14 gpio-09 ncclkrun gpio-29 vs2 gpio-49 ncbe1 gpio-10 cd1 gpio-30 ncserr gpio-50 cpar gpio-11 cad2 gpio-31 ncreq gpio-51 ncperr gpio-12 cad4 gpio-32 ncbe3 gpio-52 ncgnt gpio-13 cad6 gpio-33 nstschg gpio-53 cint gpio-14 raddr14 gpio-34 cad28 gpio-54 cclk gpio-15 cad8 gpio-35 cad30 gpio-55 nirdy gpio-16 cad10 gpio-36 cad31 gpio-56 ncbe2 gpio-17 vs1 gpio-37 cd2 gpio-57 cad18 gpio-18 cad13 gpio-38 cad20 gpio-19 cad15 gpio-39
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 147 2.13.1.15. command for cardbus table 2.120 command bit definition address : 1948_0000 bits access default description 31:9 0x0 reserved 9 ro 0x0 fast back to back enable this 1 bit field is fixed to ?0? because the bridge doesn?t support fast back to back transaction. 8 rw 0x0 cserr enable this 1 bit field is used for enabling ncserr pin interrupt. 7 rw 0x0 wait cycle control (no connection to actual block) this 1 bit field is fixed to ?0? because the bridge doesn?t support this function. 6 rw 0x1 parity error response this 1 bit field is used for enabling ncperr pin interrupt. 5 ro 0x0 vga pallet snoop enable this 1 bit field is fixed to logic 0 because the bridge doesn?t support this functionality. 4 ro 0x0 memory write invalidate enable this 1 bit field is used for enabling mwi and mrl command. 3 ro 0x0 special cycle monitoring enable this 1 bit field is fixed to logic 0 because the bridge doesn?t support this functionality. 2 ro 0x1 bus mastering enable this 1 bit field is fixed to logic 1 because the bridge always supports the master functionality. 1 ro 0x1 memory access enable this 1 bit field is fixed to logic 1 because the bridge always supports the memory area accessing.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 148 0 ro 0x1 io access enable this 1 bit field is fixed to logic 1 because the bridge always supports the i/o area accessing. 2.13.1.16. status for cardbus this register will be cleared when it is read. table 2.121 status bit definition address : 1948_0004 bits access default description 31:16 0x0 reserved 15 ro 0x0 detected parity error this 1 bit field is set when ncperr pin is asserted. 14 ro 0x0 received system error this 1 bit field is set when ncserr pin is asserted. 13 ro 0x0 received master abort this 1 bit field is set when the bridge get the master abort signaling from the pc card. 12 ro 0x0 received target abort this 1 bit field is set when the bridge get the target abort signaling from the pc card. 11 ro 0x0 signaled target abort this 1 bit field is set when the bridge make a target abort signaling. 10 ro 0x1 devsel timing this 1 bit field is fixed to 0x1 and that means the bridge operates as a medium slave. 9 ro 0x0 data parity detected this bit will be set when bridge detected parity error condition in data phase 8 ro 0x0 fast back to back capable the cardbus bridge doesn?t support fast back to back transactions.
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 149 7:0 0x00 reserved 2.13.1.17. retry time (retry) table 2.122 retry time register bit definition address : 1948_0008 bits access default description 31:9 0x0 reserved 8:4 rw 0x0 access time this 5-bit field is used for checking the latency of data. if slave failed to make valid data by the access time, then it enter to the target abort state. if this value is zero, then there is no checking for the latency of data. 3:0 rw 0x0 retry time this 4-bit field is used for limiting the number of retry. if this value is zero, then there is no limit for the retry. 7:0 0x00 reserved 2.13.1.18. clk select (csel) table 2.123 clk select register bit definition address : 1948_000c bits access default description 31:1 0x0 reserved 0 rw 0x0 divid by 4 this 1-bit field controls the cardbus clock speed. 0 = system clock/2 1 = system clock/4
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 150 3. electrical characteristics 3.1. absolute maximum ratings table 3.1 absolute maximum ratings parameter symbol rating units supply voltage (core) v ddi tbd v supply voltage (i/o) v ddp tbd v dc input current i in tbd ma operating temperature t operating 0 to 70 c storage temperature t storage c 3.2. recommended operating conditions table 3.2 recommended operating conditions parameter symbol rating units supply voltage (core) v ddi 2.5 v supply voltage (i/o) v ddp 3.3 v oscillator frequency f osc tbd mhz
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 151 3.3. dc characteristics tbd table 3.3 dc characteristics parameter symbol condition min. typ. max. unit high level input voltage v ih v low level input voltage v il v high level input current i ih a low level input current i il a high level output voltage v oh v low level output voltage v ol v tri-state output leakage current maximum operating current
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 152 3.4. ac characteristics 3.4.1. clocks sclk[x] t sclk t sclkh t sclkl t sclkf t sclkr 80% 80% 20% 20% figure 3.1 sdram clock timing mdc t mdclk t mdclkh t mdclkl t mdclkf t mdclkr 80% 80% 20% 20% figure 3.2 mdc timing (ethernet) cclk t cclk t cclkh t cclkl t cclkf t cclkr 80% 80% 20% 20% figure 3.3 spi clock timing
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 153 3.4.2. sdram timing sclk[x] addr[x] rasn casn nwe data[x] t sdad t sdrd t sdrd t sdcd t sdwd t sddd t sdcd t sdwd t sddh t sdds figure 3.4 sdram timing diagram
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 154 3.4.3. ethernet timing (mii/100mbps) rx_clk e[x]_rxdv e[x]_rxd[3:0] tx_clk e[x]_txen e[x]_txd[3:0] t ms100 t mh100 t ms100 t md100 t mh100 figure 3.5 ethernet mii timing diagram (100mbps)
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 155 3.4.4. ethernet timing (mii/10mbps) rx_clk e[x]_rxdv e[x]_rxd[3:0] tx_clk e[x]_txen e[x]_txd[3:0] t ms10 t mh10 t ms10 t md10 t mh10 figure 3.6 ethernet mii timing diagram (10mbps)
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 156 3.4.5. ethernet timing (rmii) t rs100 t rh100 ref_clk e[x]_crs_dv e[x]_rxd[1:0] t rs100 ref_clk e[x]_txen e[x]_txd[1:0] t rd100 t rh100 figure 3.7 ethernet rmii timing diagram
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 157 3.4.6. spi timing ccsn cclk cdout cdin t ccsnd t ccdod t ccdoh t ccdis t ccdih t ccsnd figure 3.8 spi timing diagram
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 158 table 3.4 a.c. electrical characteristics (ta = 0c to 70c, vdd = 3.0v to 3.3v, unit = ns) parameter description min typ max t sclk clock period for sclk - - - t sclkh clock high time for sclk - - - t sclkl clock low time for sclk - - - t sclkf clock falling time for sclk - - - t sclkr clock rising time for sclk - - - t mdclk clock period for mdc - - - t mdclkh clock high time for mdc - - - t mdclkl clock low time for mdc - - - t mdclkf clock falling time for mdc - - - t mdclkr clock rising time for mdc - - - t cclk clock period for cclk - - - t cclkh clock high time for cclk - - - t cclkl clock low time for cclk - - - t cclkf clock falling time for cclk - - - t cclkr clock rising time for cclk - - - t sdad sdram address output delay - - - t sdrd sdram ras output delay - - - t sdcd sdram cas output delay - - - t sdwd sdram we output delay - - - t sddd sdram data output delay - - - t sdds sdram data setup time - - - t sddh sdram data hold time - - - t ms100 mii setup time for 100mbps - - - t mh100 mii hold time for 100mbps - - - t md100 mii output delay for 100mbps - - - t ms10 mii setup time for 10mbps - - - t mh10 mii hold time for 10mbps - - - t md10 mii output delay for 10mbps - - - t rs100 rmii setup time - - -
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 159 t rh100 rmii hold time - - - t rd100 rmii output delay - - - t ccsnd spi delay from ccsn active to rising edge of cclk - - - t ccdod spi delay from cdout valid to rising edge of cclk - - - t ccdis spi cdin setup time - - - t ccdih spi cdin hold time - - -
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 160 4. mechanical characteristics figure 4.1 mechanical characteristics
HMS30C7110 ? 2003 magnachip semiconducto r ltd. all rights reserved version 1.5 161 5. ordering information tbd

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